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文件名称:uartnew

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  • 上传时间:
    2012-11-16
  • 文件大小:
    3.6mb
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    0次
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好用的UART通信源码,使用Verilog 编写 在QUARTUS下完成,并用ModelSim仿真通过-Source-to-use UART communications, the use of Verilog in Quartus to complete the preparation and use of ModelSim simulation through
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uartnew/clkdiv.v
uartnew/clkdiv.v.bak
uartnew/db/prev_cmp_uart_top.asm.qmsg
uartnew/db/prev_cmp_uart_top.eda.qmsg
uartnew/db/prev_cmp_uart_top.fit.qmsg
uartnew/db/prev_cmp_uart_top.map.qmsg
uartnew/db/prev_cmp_uart_top.tan.qmsg
uartnew/db/uart_top.(0).cnf.cdb
uartnew/db/uart_top.(0).cnf.hdb
uartnew/db/uart_top.(1).cnf.cdb
uartnew/db/uart_top.(1).cnf.hdb
uartnew/db/uart_top.(2).cnf.cdb
uartnew/db/uart_top.(2).cnf.hdb
uartnew/db/uart_top.(3).cnf.cdb
uartnew/db/uart_top.(3).cnf.hdb
uartnew/db/uart_top.asm.qmsg
uartnew/db/uart_top.cbx.xml
uartnew/db/uart_top.cmp.bpm
uartnew/db/uart_top.cmp.cdb
uartnew/db/uart_top.cmp.ecobp
uartnew/db/uart_top.cmp.hdb
uartnew/db/uart_top.cmp.logdb
uartnew/db/uart_top.cmp.rdb
uartnew/db/uart_top.cmp.tdb
uartnew/db/uart_top.cmp0.ddb
uartnew/db/uart_top.cmp_bb.cdb
uartnew/db/uart_top.cmp_bb.hdb
uartnew/db/uart_top.cmp_bb.logdb
uartnew/db/uart_top.cmp_bb.rcf
uartnew/db/uart_top.dbp
uartnew/db/uart_top.db_info
uartnew/db/uart_top.eco.cdb
uartnew/db/uart_top.eda.qmsg
uartnew/db/uart_top.fit.qmsg
uartnew/db/uart_top.hier_info
uartnew/db/uart_top.hif
uartnew/db/uart_top.map.bpm
uartnew/db/uart_top.map.cdb
uartnew/db/uart_top.map.ecobp
uartnew/db/uart_top.map.hdb
uartnew/db/uart_top.map.logdb
uartnew/db/uart_top.map.qmsg
uartnew/db/uart_top.map_bb.cdb
uartnew/db/uart_top.map_bb.hdb
uartnew/db/uart_top.map_bb.logdb
uartnew/db/uart_top.pre_map.cdb
uartnew/db/uart_top.pre_map.hdb
uartnew/db/uart_top.psp
uartnew/db/uart_top.pss
uartnew/db/uart_top.rtlv.hdb
uartnew/db/uart_top.rtlv_sg.cdb
uartnew/db/uart_top.rtlv_sg_swap.cdb
uartnew/db/uart_top.sgdiff.cdb
uartnew/db/uart_top.sgdiff.hdb
uartnew/db/uart_top.signalprobe.cdb
uartnew/db/uart_top.sld_design_entry.sci
uartnew/db/uart_top.sld_design_entry_dsc.sci
uartnew/db/uart_top.syn_hier_info
uartnew/db/uart_top.tan.qmsg
uartnew/db
uartnew/prev_cmp_uart_top.qmsg
uartnew/rcvr.v
uartnew/rcvr.v.bak
uartnew/simulation/modelsim/220model.v
uartnew/simulation/modelsim/altera_mf.v
uartnew/simulation/modelsim/cyclone_atoms.v
uartnew/simulation/modelsim/uart_top.vo
uartnew/simulation/modelsim/uart_top.vo.bak
uartnew/simulation/modelsim/uart_top_modelsim.xrf
uartnew/simulation/modelsim/uart_top_v.sdo
uartnew/simulation/modelsim
uartnew/simulation/myrproject.cr.mti
uartnew/simulation/myrproject.mpf
uartnew/simulation/project3.cr.mti
uartnew/simulation/project3.mpf
uartnew/simulation/timer_top/pluse_gen/verilog.psm
uartnew/simulation/timer_top/pluse_gen/_primary.dat
uartnew/simulation/timer_top/pluse_gen/_primary.vhd
uartnew/simulation/timer_top/pluse_gen
uartnew/simulation/timer_top/timer/verilog.psm
uartnew/simulation/timer_top/timer/_primary.dat
uartnew/simulation/timer_top/timer/_primary.vhd
uartnew/simulation/timer_top/timer
uartnew/simulation/timer_top/timer_tb/verilog.psm
uartnew/simulation/timer_top/timer_tb/_primary.dat
uartnew/simulation/timer_top/timer_tb/_primary.vhd
uartnew/simulation/timer_top/timer_tb
uartnew/simulation/timer_top/timer_top/verilog.psm
uartnew/simulation/timer_top/timer_top/_primary.dat
uartnew/simulation/timer_top/timer_top/_primary.vhd
uartnew/simulation/timer_top/timer_top
uartnew/simulation/timer_top/_info
uartnew/simulation/timer_top
uartnew/simulation/uart_top.xml
uartnew/simulation/uart_top_tb.v
uartnew/simulation/uart_top_tb.v.bak
uartnew/simulation/vsim.wlf
uartnew/simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.psm
uartnew/simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
uartnew/simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
uartnew/simulation/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
uartnew/simulation/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.psm
uartnew/simulation/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
uartnew/simulation/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
uartnew/simulation/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n
uartnew/simulation/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.psm
uartnew/simulation/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
uartnew/simulation/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
uartnew/simulation/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n
uartnew/simulation/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.psm
uartnew/simulation/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dat
uartnew/simulation/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.vhd
uartnew/simulation/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e
uartnew/simulation/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.psm
uartnew/simulation/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
uartnew/simulation/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
uartnew/simulation/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
uartnew/simulation/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.psm
uartnew/simulation/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
uartnew/simulation/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
uartnew/simulation/work/@l@p@m_@h@i@n@t_

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