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文件名称:RSOriginal

  • 所属分类：
    Other systems
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    11.02mb
  • 已下载：
    0次
  • 提 供 者：
    陈****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

Reed-Solomon 信道编码广泛应用于DVB中-Reed-Solomon channel coding are widely used in DVB
相关搜索： reed solomon VHDL DVB reed solomon in vhdl reed solomon vhdl 信道 dvb reed solomon

(系统自动生成,下载前可以参看下载内容)

下载文件列表

RS/code version1/ModelSim_SE/Rsdecoder/vsim.wlf
RS/code version1/ModelSim_SE/Rsdecoder/wave.do
RS/code version1/ModelSim_SE/Rsdecoder/csee.do
RS/code version1/ModelSim_SE/Rsdecoder/csee_sub.do
RS/code version1/ModelSim_SE/Rsdecoder/testbench.v
RS/code version1/ModelSim_SE/Rsdecoder/csee1.do
RS/code version1/ModelSim_SE/Rsdecoder/testbench.v~
RS/code version1/ModelSim_SE/Rsdecoder/kes.do
RS/code version1/ModelSim_SE/Rsdecoder/wave1.do
RS/code version1/ModelSim_SE/Rsdecoder/work/_info
RS/code version1/ModelSim_SE/Rsdecoder/work/@c@s@e@eblock/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/@c@s@e@eblock/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/@c@s@e@eblock/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/register8_wlh/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/register8_wlh/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/register8_wlh/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/register8_wl/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/register8_wl/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/register8_wl/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/gfadder/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/gfadder/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/gfadder/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/asyncfifo256/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/asyncfifo256/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/asyncfifo256/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/fifo_register/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/fifo_register/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/fifo_register/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/@k@e@s_block/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/@k@e@s_block/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/@k@e@s_block/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/@r@s@decoder/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/@r@s@decoder/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/@r@s@decoder/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/@s@cblock/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/@s@cblock/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/@s@cblock/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_0/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_0/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_0/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_1/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_1/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_1/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_2/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_2/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_2/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_3/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_3/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_3/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_4/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_4/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_4/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_5/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_5/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_5/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_6/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_6/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_6/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_7/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_7/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_7/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_8/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_8/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_8/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_9/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_9/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_9/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_10/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_10/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_10/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_11/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_11/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_11/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_12/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_12/verilog.asm
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_12/_primary.dat
RS/code version1/ModelSim_SE/Rsdecoder/work/syndcell_13/_primary.vhd
RS/code version1/ModelSim_SE/Rsdecoder/work/syndc

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