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文件名称:RGBtoYCbCr

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [Excel]
  • 上传时间：
    2012-11-16
  • 文件大小：
    402.09kb
  • 已下载：
    0次
  • 提 供 者：
    Jac****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.

-FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.
相关搜索： RGBtoYCbCr Color Space conversion verilog RGB to Y cbcr

(系统自动生成,下载前可以参看下载内容)

下载文件列表

Readme.txt
RGBColorBars_testvectors.xls
Verilog/
Verilog/CSC/
Verilog/CSC/CSC.npl
Verilog/CSC/csc_top.ucf
Verilog/CSC/csc_top_tb.udo
Verilog/CSC/wave_all_csc_top_tb.do
Verilog/Hdl/
Verilog/Hdl/const_mult.v
Verilog/Hdl/csc.v
Verilog/Hdl/csc_top.v
Verilog/Hdl/csc_top_tb.tf
VHDL/
VHDL/CSC/
VHDL/CSC/CSC.npl
VHDL/CSC/csc_top.ucf
VHDL/CSC/csc_top_tb.udo
VHDL/CSC/wave_all_csc_top_tb.do
VHDL/Hdl/
VHDL/Hdl/const_mult.vhd
VHDL/Hdl/csc.vhd
VHDL/Hdl/csc_top.vhd
VHDL/Hdl/csc_top_tb.vhd
VHDL/Top/
VHDL/Top/netlist_10bit_13-11-10bit/
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2/
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2E/
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2E/compile.cmd
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2E/csc_top.bld
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2E/csc_top.par
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2E/csc_top.pcf
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2E/csc_top.ucf
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2E/csc_top_map.mrp
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2/compile.cmd
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2/csc_top.bld
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2/csc_top.par
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2/csc_top.pcf
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2/csc_top.ucf
VHDL/Top/netlist_10bit_13-11-10bit/Spartan2/csc_top_map.mrp
VHDL/Top/netlist_10bit_13-11-10bit/Virtex/
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2/
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2Pro/
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2Pro/compile.cmd
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2Pro/csc_top.bld
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2Pro/csc_top.par
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2Pro/csc_top.pcf
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2Pro/csc_top.ucf
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2Pro/csc_top_map.mrp
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2/compile.cmd
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2/csc_top.bld
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2/csc_top.par
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2/csc_top.pcf
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2/csc_top.ucf
VHDL/Top/netlist_10bit_13-11-10bit/Virtex2/csc_top_map.mrp
VHDL/Top/netlist_10bit_13-11-10bit/VirtexE/
VHDL/Top/netlist_10bit_13-11-10bit/VirtexE/compile.cmd
VHDL/Top/netlist_10bit_13-11-10bit/VirtexE/csc_top.bld
VHDL/Top/netlist_10bit_13-11-10bit/VirtexE/csc_top.par
VHDL/Top/netlist_10bit_13-11-10bit/VirtexE/csc_top.pcf
VHDL/Top/netlist_10bit_13-11-10bit/VirtexE/csc_top.ucf
VHDL/Top/netlist_10bit_13-11-10bit/VirtexE/csc_top_map.mrp
VHDL/Top/netlist_10bit_13-11-10bit/Virtex/compile.cmd
VHDL/Top/netlist_10bit_13-11-10bit/Virtex/csc_top.bld
VHDL/Top/netlist_10bit_13-11-10bit/Virtex/csc_top.par
VHDL/Top/netlist_10bit_13-11-10bit/Virtex/csc_top.pcf
VHDL/Top/netlist_10bit_13-11-10bit/Virtex/csc_top.ucf
VHDL/Top/netlist_10bit_13-11-10bit/Virtex/csc_top_map.mrp
VHDL/Top/netlist_10bit_13-11-10bit/Virtex/csc_top_virtex.ucf
VHDL/Top/netlist_10bit_13-11-10bit/Virtex/mppr.par
VHDL/Top/netlist_10bit_8bit/
VHDL/Top/netlist_10bit_8bit/Spartan2/
VHDL/Top/netlist_10bit_8bit/Spartan2E/
VHDL/Top/netlist_10bit_8bit/Spartan2E/compile.cmd
VHDL/Top/netlist_10bit_8bit/Spartan2E/csc_top.bld
VHDL/Top/netlist_10bit_8bit/Spartan2E/csc_top.par
VHDL/Top/netlist_10bit_8bit/Spartan2E/csc_top.pcf
VHDL/Top/netlist_10bit_8bit/Spartan2E/csc_top.ucf
VHDL/Top/netlist_10bit_8bit/Spartan2E/csc_top_map.mrp
VHDL/Top/netlist_10bit_8bit/Spartan2/compile.cmd
VHDL/Top/netlist_10bit_8bit/Spartan2/csc_top.bld
VHDL/Top/netlist_10bit_8bit/Spartan2/csc_top.par
VHDL/Top/netlist_10bit_8bit/Spartan2/csc_top.pcf
VHDL/Top/netlist_10bit_8bit/Spartan2/csc_top.ucf
VHDL/Top/netlist_10bit_8bit/Spartan2/csc_top_map.mrp
VHDL/Top/netlist_10bit_8bit/Virtex/
VHDL/Top/netlist_10bit_8bit/Virtex2/
VHDL/Top/netlist_10bit_8bit/Virtex2Pro/
VHDL/Top/netlist_10bit_8bit/Virtex2Pro/compile.cmd
VHDL/Top/netlist_10bit_8bit/Virtex2Pro/csc_top.bld
VHDL/Top/netlist_10bit_8bit/Virtex2Pro/csc_top.par
VHDL/Top/netlist_10bit_8bit/Virtex2Pro/csc_top.pcf
VHDL/Top/netlist_10bit_8bit/Virtex2Pro/csc_top.ucf
VHDL/Top/netlist_10bit_8bit/Virtex2Pro/csc_top_map.mrp
VHDL/Top/netlist_10bit_8bit/Virtex2/compile.cmd
VHDL/Top/netlist_10bit_8bit/Virtex2/csc_top.bld
VHDL/Top/netlist_10bit_8bit/Virtex2/csc_top.par
VHDL/Top/netlist_10bit_8bit/Virtex2/csc_top.pcf
VHDL/Top/netlist_10bit_8bit/Virtex2/csc_top.ucf
VHDL/Top/netlist_10bit_8bit/Virtex2/csc_top_map.mrp
VHDL/Top/netlist_10bit_8bit/VirtexE/
VHDL/Top/netlist_10bit_8bit/VirtexE/compile.cmd
VHDL/Top/netlist_10bit_8bit/VirtexE/csc_top.bld
VHDL/Top/netlist_10bit_8bit/VirtexE/csc_top.par
VHDL/Top/netlist_10bit_8bit/VirtexE/csc_top.pcf
VHDL/Top/netlist_10bit_8bit/VirtexE/csc_top.ucf
VHDL/Top/netlist_10bit_8bit/VirtexE/csc_top_map.mrp
VHDL/Top/netlist_10bit_8bit/Virtex/compile.cmd
VHDL/Top/netlist_10bit_8bit/Virtex/csc_top.bld
VHDL/Top/netlist_10bit_8bit/Virtex/csc_top.par
VHDL/Top/netlist_10bit_8bit/Virtex/csc_top.pcf
VHDL/Top/netlist_10bit_8bit/Virtex/csc_top.ucf
VHDL/Top/netlist_10bit_8bit/Virtex/csc_top_map.mrp
VHDL/Top/netlist_8bit_13-11-10bit/
VHDL/Top/netlist_8bit_13-11-10bit/Spartan2/
VHDL/Top/netlist_8bit_13-11-10bit/Spartan2E/
VHDL/Top/netlist_8b

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