文件名称:uart01
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- 上传时间:2012-11-16
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文件大小:136.69kb
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一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序-A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure
相关搜索: RS232 interface vhdl
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下载文件列表
uart01/__projnav/uart01.gfl
uart01/__projnav/sumrpt_tcl.rsp
uart01/__projnav/runXst_tcl.rsp
uart01/__projnav/uart01_flowplus.gfl
uart01/__projnav/top.xst
uart01/uart01.ise
uart01/tb_uart.vhw
uart01/tb_uart.ant
uart01/tb_uart_bencher.prj
uart01/tb_uart.jhd
uart01/uart01.ise_ISE_Backup
uart01/uart.vhd
uart01/baud.vhd
uart01/reciever.vhd
uart01/transfer.vhd
uart01/pepExtractor.prj
uart01/top_summary.html
uart01/__projnav.log
uart01/automake.log
uart01/top.prj
uart01/top.cmd_log
uart01/top.syr
uart01/top.lso
uart01/xst/work/sub00/vhpl00.vho
uart01/xst/work/sub00/vhpl01.vho
uart01/xst/work/sub00/vhpl02.vho
uart01/xst/work/sub00/vhpl03.vho
uart01/xst/work/sub00/vhpl04.vho
uart01/xst/work/sub00/vhpl05.vho
uart01/xst/work/sub00/vhpl06.vho
uart01/xst/work/sub00/vhpl07.vho
uart01/xst/work/hdllib.ref
uart01/xst/work/hdpdeps.ref
uart01/top.ngr
uart01/top.ngc
uart01/top.stx
uart01/tb_uart.xwv_bak
uart01/tb_uart.tbw
uart01/tb_uart.udo
uart01/tb_uart.fdo
uart01/transcript
uart01/work/_info
uart01/work/baud/_primary.dat
uart01/work/baud/behavioral.dat
uart01/work/baud/behavioral.asm
uart01/work/reciever/_primary.dat
uart01/work/reciever/behavioral.dat
uart01/work/reciever/behavioral.asm
uart01/work/transfer/_primary.dat
uart01/work/transfer/behavioral.dat
uart01/work/transfer/behavioral.asm
uart01/work/top/_primary.dat
uart01/work/top/behavioral.dat
uart01/work/top/behavioral.asm
uart01/work/tb_uart/_primary.dat
uart01/work/tb_uart/testbench_arch.dat
uart01/work/tb_uart/testbench_arch.asm
uart01/results.txt
uart01/vsim.wlf
uart01/uart01.dhp
uart01/__ISE_repository_uart01.ise_.lock
uart01/xst/dump.xst/top.prj/ngx/opt
uart01/xst/dump.xst/top.prj/ngx/notopt
uart01/xst/dump.xst/top.prj/ngx
uart01/xst/work/sub00
uart01/xst/dump.xst/top.prj
uart01/xst/work
uart01/xst/dump.xst
uart01/work/baud
uart01/work/reciever
uart01/work/transfer
uart01/work/top
uart01/work/tb_uart
uart01/_xmsgs
uart01/__projnav
uart01/xst
uart01/work
uart01
uart01/__projnav/sumrpt_tcl.rsp
uart01/__projnav/runXst_tcl.rsp
uart01/__projnav/uart01_flowplus.gfl
uart01/__projnav/top.xst
uart01/uart01.ise
uart01/tb_uart.vhw
uart01/tb_uart.ant
uart01/tb_uart_bencher.prj
uart01/tb_uart.jhd
uart01/uart01.ise_ISE_Backup
uart01/uart.vhd
uart01/baud.vhd
uart01/reciever.vhd
uart01/transfer.vhd
uart01/pepExtractor.prj
uart01/top_summary.html
uart01/__projnav.log
uart01/automake.log
uart01/top.prj
uart01/top.cmd_log
uart01/top.syr
uart01/top.lso
uart01/xst/work/sub00/vhpl00.vho
uart01/xst/work/sub00/vhpl01.vho
uart01/xst/work/sub00/vhpl02.vho
uart01/xst/work/sub00/vhpl03.vho
uart01/xst/work/sub00/vhpl04.vho
uart01/xst/work/sub00/vhpl05.vho
uart01/xst/work/sub00/vhpl06.vho
uart01/xst/work/sub00/vhpl07.vho
uart01/xst/work/hdllib.ref
uart01/xst/work/hdpdeps.ref
uart01/top.ngr
uart01/top.ngc
uart01/top.stx
uart01/tb_uart.xwv_bak
uart01/tb_uart.tbw
uart01/tb_uart.udo
uart01/tb_uart.fdo
uart01/transcript
uart01/work/_info
uart01/work/baud/_primary.dat
uart01/work/baud/behavioral.dat
uart01/work/baud/behavioral.asm
uart01/work/reciever/_primary.dat
uart01/work/reciever/behavioral.dat
uart01/work/reciever/behavioral.asm
uart01/work/transfer/_primary.dat
uart01/work/transfer/behavioral.dat
uart01/work/transfer/behavioral.asm
uart01/work/top/_primary.dat
uart01/work/top/behavioral.dat
uart01/work/top/behavioral.asm
uart01/work/tb_uart/_primary.dat
uart01/work/tb_uart/testbench_arch.dat
uart01/work/tb_uart/testbench_arch.asm
uart01/results.txt
uart01/vsim.wlf
uart01/uart01.dhp
uart01/__ISE_repository_uart01.ise_.lock
uart01/xst/dump.xst/top.prj/ngx/opt
uart01/xst/dump.xst/top.prj/ngx/notopt
uart01/xst/dump.xst/top.prj/ngx
uart01/xst/work/sub00
uart01/xst/dump.xst/top.prj
uart01/xst/work
uart01/xst/dump.xst
uart01/work/baud
uart01/work/reciever
uart01/work/transfer
uart01/work/top
uart01/work/tb_uart
uart01/_xmsgs
uart01/__projnav
uart01/xst
uart01/work
uart01
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