LCD/UART_PC_to_LCD/smartgen/PLL_1M/PLL_1M.gen
LCD/UART_PC_to_LCD/smartgen/PLL_1M/PLL_1M.log
LCD/UART_PC_to_LCD/smartgen/PLL_1M/PLL_1M.v
LCD/UART_PC_to_LCD/smartgen/PLL_1M/PLL_1M.cxf
LCD/UART_PC_to_LCD/smartgen/PLL_1M_work.ixf
LCD/UART_PC_to_LCD/smartgen/smartgen.aws
LCD/UART_PC_to_LCD/hdl/Clock_Gen.v
LCD/UART_PC_to_LCD/hdl/LCD_Driver.v
LCD/UART_PC_to_LCD/hdl/UART_PC_to_LCD.v
LCD/UART_PC_to_LCD/hdl/rec.v
LCD/UART_PC_to_LCD/viewdraw/vf/project.lst
LCD/UART_PC_to_LCD/viewdraw/viewdraw.ini
LCD/UART_PC_to_LCD/simulation/modelsim.ini.sav
LCD/UART_PC_to_LCD/simulation/modelsim.ini
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.srs
LCD/UART_PC_to_LCD/synthesis/stdout.log
LCD/UART_PC_to_LCD/synthesis/syntmp/UART_PC_to_LCD.plg
LCD/UART_PC_to_LCD/synthesis/syntmp/UART_PC_to_LCD.msg
LCD/UART_PC_to_LCD/synthesis/backup/UART_PC_to_LCD.srr
LCD/UART_PC_to_LCD/synthesis/run_options.txt
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.srr
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.tlg
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD_syn.prj
LCD/UART_PC_to_LCD/synthesis/traplog.tlg
LCD/UART_PC_to_LCD/synthesis/.recordref
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.srd
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.srm
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.map
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.edn
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.sdf
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD_sdc.sdc
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.so
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD.areasrr
LCD/UART_PC_to_LCD/synthesis/UART_PC_to_LCD_drc.rpt
LCD/UART_PC_to_LCD/stimulus/UART_PC_to_LCD.hpj
LCD/UART_PC_to_LCD/stimulus/waveperl.log
LCD/UART_PC_to_LCD/stimulus/BtimErrors.log
LCD/UART_PC_to_LCD/stimulus/files_to_build.txt
LCD/UART_PC_to_LCD/stimulus/UART_PC_to_LCD.dsk
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD.tcl
LCD/UART_PC_to_LCD/designer/impl1/designer_genhdl.log
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD.ide_des
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD.dtf/verify.log
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD.pdb
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD.pdb.depends
LCD/UART_PC_to_LCD/designer/impl1/designer.log
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD_fp/UART_PC_to_LCD.pro
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD_fp/$$FlashPro_09430.L$$
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD_fp/UART_PC_to_LCD.log
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD_fp/projectData/UART_PC_to_LCD.pdb
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD_ba.sdf
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD_ba.v
LCD/UART_PC_to_LCD/designer/impl1/designer_gen_ba.log
LCD/UART_PC_to_LCD/designer/impl1/UART_PC_to_LCD.adb
LCD/UART_PC_to_LCD/UART_PC_to_LCD.prj
LCD/PC_to_LCD/smartgen/PLL_2M/PLL_2M.gen
LCD/PC_to_LCD/smartgen/PLL_2M/PLL_2M.log
LCD/PC_to_LCD/smartgen/PLL_2M/PLL_2M.v
LCD/PC_to_LCD/smartgen/PLL_2M/PLL_2M.cxf
LCD/PC_to_LCD/smartgen/PLL_2M_work.ixf
LCD/PC_to_LCD/smartgen/wr_FIFO/wr_FIFO.gen
LCD/PC_to_LCD/smartgen/wr_FIFO/wr_FIFO.log
LCD/PC_to_LCD/smartgen/wr_FIFO/wr_FIFO.v
LCD/PC_to_LCD/smartgen/wr_FIFO/wr_FIFO.cxf
LCD/PC_to_LCD/smartgen/wr_FIFO_work.ixf
LCD/PC_to_LCD/smartgen/smartgen.aws
LCD/PC_to_LCD/hdl/rec.v
LCD/PC_to_LCD/hdl/stateMW.v
LCD/PC_to_LCD/hdl/PC_to_LCD.v
LCD/PC_to_LCD/hdl/LCD_Driver.v
LCD/PC_to_LCD/hdl/data_Latch.v
LCD/PC_to_LCD/hdl/stateMR.v
LCD/PC_to_LCD/hdl/Clock_Gen.v
LCD/PC_to_LCD/viewdraw/vf/project.lst
LCD/PC_to_LCD/viewdraw/viewdraw.ini
LCD/PC_to_LCD/simulation/RAM256X8_R0C0.mem
LCD/PC_to_LCD/simulation/modelsim.ini.sav
LCD/PC_to_LCD/simulation/modelsim.ini
LCD/PC_to_LCD/synthesis/PC_to_LCD.srs
LCD/PC_to_LCD/synthesis/stdout.log
LCD/PC_to_LCD/synthesis/syntmp/PC_to_LCD.plg
LCD/PC_to_LCD/synthesis/syntmp/PC_to_LCD.msg
LCD/PC_to_LCD/synthesis/backup/PC_to_LCD.srr
LCD/PC_to_LCD/synthesis/run_options.txt
LCD/PC_to_LCD/synthesis/PC_to_LCD.srr
LCD/PC_to_LCD/synthesis/PC_to_LCD.tlg
LCD/PC_to_LCD/synthesis/PC_to_LCD_syn.prj
LCD/PC_to_LCD/synthesis/traplog.tlg
LCD/PC_to_LCD/synthesis/.recordref
LCD/PC_to_LCD/synthesis/PC_to_LCD.srd
LCD/PC_to_LCD/synthesis/PC_to_LCD.srm
LCD/PC_to_LCD/synthesis/PC_to_LCD.map
LCD/PC_to_LCD/synthesis/PC_to_LCD.edn
LCD/PC_to_LCD/synthesis/PC_to_LCD.sdf
LCD/PC_to_LCD/synthesis/PC_to_LCD_sdc.sdc
LCD/PC_to_LCD/synthesis/PC_to_LCD.so
LCD/PC_to_LCD/synthesis/PC_to_LCD.areasrr
LCD/PC_to_LCD/synthesis/PC_to_LCD_drc.rpt
LCD/PC_to_LCD/stimulus/PC_to_LCD.hpj
LCD/PC_to_LCD/stimulus/waveperl.log
LCD/PC_to_LCD/stimulus/BtimErrors.log
LCD/PC_to_LCD/stimulus/files_to_build.txt
LCD/PC_to_LCD/stimulus/PC_to_LCD.dsk
LCD/PC_to_LCD/designer/impl1/PC_to_LCD.tcl
LCD/PC_to_LCD/designer/impl1/PC_to_LCD_1_1_fp_7/PC_to_LCD_1.pro
LCD/PC_to_LCD/designer/impl1/PC_to_LCD_1_1_fp_7/$$FlashPro_09430.L$$
LCD/PC_to_LCD/designer/impl1/PC_to_LCD_1_1_fp_7/projectData/PC_to_LCD_1.pdb
LCD/PC_to_LCD/designer/impl1/PC_to_LCD_1_1_fp_7/PC_to_LCD_1.log
LCD/PC_to_LCD/designer/impl1/designer_genhdl.log
LCD/PC_to_LCD/designer/impl1/PC_to_LCD.ide_des
LCD/PC_to_LCD/designer/impl1/designer_gen_ba.log
LCD/PC_to_LCD/designer/impl1/PC_to_LCD_1_ba.sdf
LCD/PC_to_LCD/designer/impl1/PC_to_LCD.dtf/verify.log
LCD/PC_to_LCD