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文件名称:VerilogHDL

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    19.02mb
  • 已下载：
    0次
  • 提 供 者：
    q****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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Verilog HDL 程序设计实例详解

Verilog HDL 程序设计实例详解-Verilog HDL programming example explanation example explanation of Verilog HDL programming
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Chapter-1/adder/adder.cr.mti
Chapter-1/adder/adder.mpf
Chapter-1/adder/adder.v
Chapter-1/adder/adder_testbench.do
Chapter-1/adder/adder_testbench.v
Chapter-1/adder/chart/图1-3.bmp
Chapter-1/adder/chart/图1-4.bmp
Chapter-1/adder/chart/图1-5.bmp
Chapter-1/adder/chart/图1-6.bmp
Chapter-1/adder/chart/图1-7.bmp
Chapter-1/adder/chart/图1-8.bmp
Chapter-1/adder/transcript
Chapter-1/adder/vsim.wlf
Chapter-1/adder/work/adder/transcript
Chapter-1/adder/work/adder/verilog.txt.asm
Chapter-1/adder/work/adder/_primary.dat
Chapter-1/adder/work/adder/_primary.vhd
Chapter-1/adder/work/adder_testbench/verilog.asm
Chapter-1/adder/work/adder_testbench/_primary.dat
Chapter-1/adder/work/adder_testbench/_primary.vhd
Chapter-1/adder/work/_info
Chapter-2/2.1/adder
Chapter-2/2.1/adder.cr.mti
Chapter-2/2.1/adder.mpf
Chapter-2/2.1/adder.v
Chapter-2/2.1/adder_testbench.v
Chapter-2/2.1/chart/图2-2.bmp
Chapter-2/2.1/chart/表2-1.bmp
Chapter-2/2.1/transcript
Chapter-2/2.1/vsim.wlf
Chapter-2/2.1/wave/adder.bmp
Chapter-2/2.1/wave/adder_testbench.bmp
Chapter-2/2.1/work/adder/verilog.asm
Chapter-2/2.1/work/adder/_primary.dat
Chapter-2/2.1/work/adder/_primary.vhd
Chapter-2/2.1/work/adder_testbench/verilog.asm
Chapter-2/2.1/work/adder_testbench/_primary.dat
Chapter-2/2.1/work/adder_testbench/_primary.vhd
Chapter-2/2.1/work/_info
Chapter-2/2.2/chart/图2-4.bmp
Chapter-2/2.2/chart/表2-2.bmp
Chapter-2/2.2/full_add.cr.mti
Chapter-2/2.2/full_add.mpf
Chapter-2/2.2/full_add.v
Chapter-2/2.2/full_add_testbench.v
Chapter-2/2.2/transcript
Chapter-2/2.2/vsim.wlf
Chapter-2/2.2/wave/full_add.bmp
Chapter-2/2.2/wave/full_add_testbench.bmp
Chapter-2/2.2/work/full_add/verilog.asm
Chapter-2/2.2/work/full_add/_primary.dat
Chapter-2/2.2/work/full_add/_primary.vhd
Chapter-2/2.2/work/full_add_testbench/verilog.asm
Chapter-2/2.2/work/full_add_testbench/_primary.dat
Chapter-2/2.2/work/full_add_testbench/_primary.vhd
Chapter-2/2.2/work/_info
Chapter-2/2.3/adder4.cr.mti
Chapter-2/2.3/adder4.mpf
Chapter-2/2.3/adder4.v
Chapter-2/2.3/adder4_testbench.v
Chapter-2/2.3/chart/图2-7.bmp
Chapter-2/2.3/transcript
Chapter-2/2.3/vsim.wlf
Chapter-2/2.3/wave/adder4.bmp
Chapter-2/2.3/wave/adder4_testbench.bmp
Chapter-2/2.3/work/adder4/verilog.asm
Chapter-2/2.3/work/adder4/_primary.dat
Chapter-2/2.3/work/adder4/_primary.vhd
Chapter-2/2.3/work/adder4_testbench/verilog.asm
Chapter-2/2.3/work/adder4_testbench/_primary.dat
Chapter-2/2.3/work/adder4_testbench/_primary.vhd
Chapter-2/2.3/work/_info
Chapter-2/2.4/chart/图2-10.bmp
Chapter-2/2.4/coun4_testbench.v
Chapter-2/2.4/count4.cr.mti
Chapter-2/2.4/count4.mpf
Chapter-2/2.4/count4.v
Chapter-2/2.4/transcript
Chapter-2/2.4/vsim.wlf
Chapter-2/2.4/wave/coun4.bmp
Chapter-2/2.4/wave/coun4_testbench.bmp
Chapter-2/2.4/work/coun4_testbench/verilog.asm
Chapter-2/2.4/work/coun4_testbench/_primary.dat
Chapter-2/2.4/work/coun4_testbench/_primary.vhd
Chapter-2/2.4/work/count4/verilog.asm
Chapter-2/2.4/work/count4/_primary.dat
Chapter-2/2.4/work/count4/_primary.vhd
Chapter-2/2.4/work/_info
Chapter-2/2.5/chart/图2-12.bmp
Chapter-2/2.5/chart/表2-3.bmp
Chapter-2/2.5/count60.cr.mti
Chapter-2/2.5/count60.mpf
Chapter-2/2.5/count60.v
Chapter-2/2.5/count60_testbench.v
Chapter-2/2.5/transcript
Chapter-2/2.5/vsim.wlf
Chapter-2/2.5/wave/count60.bmp
Chapter-2/2.5/wave/count60_testbench.bmp
Chapter-2/2.5/work/count60/verilog.asm
Chapter-2/2.5/work/count60/_primary.dat
Chapter-2/2.5/work/count60/_primary.vhd
Chapter-2/2.5/work/count60_testbench/verilog.asm
Chapter-2/2.5/work/count60_testbench/_primary.dat
Chapter-2/2.5/work/count60_testbench/_primary.vhd
Chapter-2/2.5/work/_info
Chapter-3/3.1/add_tree_mult.cr.mti
Chapter-3/3.1/add_tree_mult.mpf
Chapter-3/3.1/add_tree_mult.v
Chapter-3/3.1/add_tree_mult_testbench.v
Chapter-3/3.1/chart/图3-2.bmp
Chapter-3/3.1/transcript
Chapter-3/3.1/vsim.wlf
Chapter-3/3.1/wave/add_tree_mult.bmp
Chapter-3/3.1/wave/add_tree_mult_testbench.bmp
Chapter-3/3.1/work/add_tree_mult/verilog.asm
Chapter-3/3.1/work/add_tree_mult/_primary.dat
Chapter-3/3.1/work/add_tree_mult/_primary.vhd
Chapter-3/3.1/work/add_tree_mult_testbench/verilog.asm
Chapter-3/3.1/work/add_tree_mult_testbench/_primary.dat
Chapter-3/3.1/work/add_tree_mult_testbench/_primary.vhd
Chapter-3/3.1/work/_info
Chapter-3/3.2/chart/图3-5.bmp
Chapter-3/3.2/chart/图3-6.bmp
Chapter-3/3.2/chart/表3-1.bmp
Chapter-3/3.2/lookup_mult.cr.mti
Chapter-3/3.2/lookup_mult.mpf
Chapter-3/3.2/lookup_mult.v
Chapter-3/3.2/lookup_mult_testbench.v
Chapter-3/3.2/transcript
Chapter-3/3.2/vsim.wlf
Chapter-3/3.2/wave/lookup.bmp
Chapter-3/3.2/wave/lookup_mult.bmp
Chapter-3/3.2/wave/lookup_mult_testbench.bmp
Chapter-3/3.2/work/lookup/verilog.asm
Chapter-3/3.2/work/lookup/_primary.dat
Chapter-3/3.2/work/lookup/_primary.vhd
Chapter-3/3.2/work/lookup_mult/verilog.asm
Chapter-3/3.2/work/lookup_mult/_primary.dat
Chapter-3/3.2/work/lookup_mult/_primary.vhd
Chapter-3/3.2/work/lookup_mult_testbench/verilog.asm
Chapter-3/3.2/work/lookup_mult_testbench/_primary.dat
Chapter-3/3.2/work/lookup_mult_testbench/_primary.vhd
Chapter-3/3.2/work/_info
Chapter-3/3.3/chart/图3-8.bmp
Chapter-3/3.3/chart/图3-9.bmp
Chapter-3/3.3/mult_Booth.cr.mti
Chapter-3/3.3/mult_Booth.mpf
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