搜索资源列表
serial
- 用VHDL实现串口与电脑通信,已调试过,没错误-it can be used to commuciate serial with computer
mc8051_siu
- mc8051中 源码串口单元输入输出vhdl语言设计-mc8051 vhdl code, Descr iption: Serial interface unit for the mc8051 microcontroller.
UART
- 异步串口收发程序,波特率4800。VHDL写成。在ALTERA开发板上测试成功。-This is a UART program, with a fixed 4800bps. Tested successfully on an Altera divice.
nios_ck
- VHDL的小例子,DE2开发板的入门例子,一个基于SOPC的串口的例子。- VHDL example, the entry of the DE2 development board example of a SOPC-based serial port examples.
ISE-chuankou
- 基于FPGA的串口通讯程序,用VHDL语言编写,用ISE平台编译,并且用串口调试助手和PC机通讯准备无误!-FPGA-based serial communication program using VHDL language, compiled with ISE platform, ready to correct and serial debugging aides and PC communication!
baud
- UART 异步通信串口协议的VHDL实现包括3个基本模块:时钟分频、接收模块和发送模块-UART asynchronous serial interface protocol VHDL consists of three basic modules: clock divider, the receiver module and transmit module
uart_altera
- 本程序使用vhdl语言编写,能够实现ALTERA CPLD-EPM3128A与PC机之间的串口通讯功能。-This program written in vhdl language of ALTERA the CPLD-EPM3128A between PC and the serial communication function.
atel2_bin
- 串行口 VHDL 嵌入式 单片机 串行接口实现-serial port
Rwummayiie
- 研究了传统误码仪的工作原理与结构,并运用VHDL语言在FPGA芯片上模拟实现了绝大部分的传统误码仪的功能,,如LCD显示出来驱动driver,串口通信驱动driver,误码测试,数据存储芯片驱动driver等功能. -Study the working principle and structure of the traditional BERT, and the use of VHDL language to simulate most of the traditional BERT fu
VVHDL_32bit_tH
- VHDL写的32位计数,两个四位共阳数码管输出串口输出+数码码管显示的计时器程序每次停止后串口输出。,已通过测试。 -VHDL written 32 count, two four sun digital serial output tube output serial output the+ digital code to display the timer program each stop. , Has been tested.
T51
- 免费的8051 VHDL 原码。很好的风格。 完整的说明和模拟环境。 实现后的面积很小,速度很高。我比较过这个码与商业的产品, 毫不逊色,在速度上还略有优势。 验证过了串口,输出入口,定时单元及运算单元。 -Free 8051 VHDL source. Good style. Complete descr iption and simulation environment. After achieving the small size of the high speed. I have comp
my_uart
- 使用VHDL描述的简单的串口通讯,在Quartus上验证过,包含所有文件-this is a simple uart
uartrxd
- 用VHDL硬件描述语言实现了串口的基本收发功能,能够在FPGA上正常运行-VHDL hardware descr iption language with a basic transceiver serial port function, able to run properly on FPGA
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
uart
- uart串口通讯,波特率任意可调,采用vhdl语言编写,ise和quartus均可使用-uart serial communication baud rate of any adjustable
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
uart_rx
- 用VHDL语言实现的Uart串口通信程序。在xilinx公司FPGA芯片验证过。-Uart serial communication program using VHDL. Validation in xilinx Company FPGA chip.
chuankoufasong
- 可以实现FPGA的串口发送与接收的vhdl程序-Can to achieve the FPGA serial interface to send and receive the vhdl program
Recv
- 运用VHDL语言,实现串口的接收子程序,可以将该子模块加载到主程序中。-VHDL UART RECEIVE
baud_gen
- 运用VHDL语言,实现串口收发程序中的波特率设置的子程序,可以将该子模块加载到主程序中。-VHDL language, set the baud rate of the serial transceiver subroutine, this sub-module is loaded into the main program.