搜索资源列表
595-164
- 基于C的595-164的使用,内涵功能仿真图-The use of C-based 595-164, meaning functional simulation map
VB_CNC
- 利用VB程序实现数控系统的刀具半径补偿功能仿真模拟。包括直线对直线,直线对圆弧,圆弧对直线,圆弧对圆弧的实现。-Using VB program numerical control system simulation tool radius compensation. Include lines of straight line with the arc, the arc of the straight line, arc of the arc is achieved.
counter10
- verilog编写的10进制计数器,并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
MP3fangzhen
- map3的小程序,实现map3功能仿真,源程序直接进行编译即可-map3 a small program to achieve map3 functional simulation, source code can be compiled directly
doppler_radar
- 脉冲多普勒雷达发射和接收功能仿真mdl文件-doppler radar tran and rcv simutlation
pseudo8
- 8位伪随机序列发生器设计,可以进行时序仿真和功能仿真-The design of 8 bits Pseudo-Random Binary Sequence,you can do Timing simulation and function simulation
Uart
- 用Verilog实现简单的串口通信,经过功能仿真和板上调试,接收和发送模块均无问题-Using Verilog realize a simple serial communication, through functional simulation and on-board debugging, had no problems receiving and sending module
Exp_golomb_enc_p8
- 指数哥伦布编码模块,数据编码后8位为一个单元输出,该模块功能仿真可以,但为综合调试过,下载者可参考设计思想-Index Columbus coding module, the data is encoded as a unit 8 outputs, the module functional simulation can be, but is integrated debugging, and downloads may reference design ideas
RS_CODEC_v6
- 超宽带系统中RS编码模块的功能仿真,使用C语言实现。-C platform for RS coding in UWB system.
UART_FIFO
- 用VHDL语言实现内置FIFO的UART,并做时序仿真和功能仿真确定正确与否。-Implement a built in FIFO UART using VHDL language, and do functional simulation and timing simulation to determine correct.
FIFO
- 用VHDL语言实现一种异步FIFO,并做时序仿真和功能仿真检验正确性。-Achieve an asynchronous FIFO using VHDL language, and do functional simulation and timing simulation test accuracy.
traffic-light
- 可以实现简单路口交通灯的功能仿真,用于学生实验仿真-Can achieve a simple traffic light intersection functional simulation, simulation experiments for students
pcm
- 基于system viwe的pcm编译码功能仿真-Functional simulation based the system viwe pcm codec
Example-b3-1
- “\Example-b3-1\uart_regs\src”目录下为设计源文件 “\Example-b3-1\uart_regs\core”目录下为Altera的IP宏功能模块 “\Example-b3-1\uart_regs\sim\funcsim”目录下为功能仿真文件 “\Example-b3-1\uart_regs\sim\parsim”目录下为时序仿真文件 “\Example-b3-1\uart_regs\de
Example-b8-1
- 使用ModelSim对Altera设计进行功能仿真的简要操作步骤 1.建立仿真工程 2.Altera仿真库的编译与映射 3.编译HDL源代码和Testbench 4.启动仿真器并加载设计顶层 5.打开观测窗口,添加信号 6.执行仿真-Using ModelSim Altera design for functional simulation brief Procedure 1. Create a simulation project Compilation and map
swp
- 本文用Verilog语言设计实现SWP数字收发接口的电路设计,并用QuartusⅡ9.1完成调试和功能仿真。在我们的设计中,采用的是分模块的设计方法。设计过程中,我们将首先完成系统架构设计,明确各个分模块的功能。分别实现各模块功能后,再联合所有模块进行总体系统的调试和仿真,最终完成SWP数字收发接口的模块设计。-SWP paper implements digital transceiver interface circuit design using Verilog language desi
trafficlight
- 本课程设计侧重于逻辑电路设计同时采用VHDL硬件描述语言辅助完成对十字路口交通灯的功能仿真。在设计过程中,重点探讨了交通灯控制系统的设计思路和功能模块的划分,对设计过程中出现的问题详细进行。系统主要由四个模块组成:时钟分频模块、交通灯的控制及计时模块、扫描显示译码模块。-This course is designed to focus on the logic design using VHDL hardware descr iption language at the same time as
matlab
- 完成4GLTE的小区搜索,及上下行数据传输功能仿真-4GLTE complete cell search, and downlink data transmission function simulation
fir
- 滤波器:一款8阶的fir串型滤波器,已近通过功能仿真-Filters: an 8-order fir string type filter, almost by functional simulation
FIFO1
- 给出一个位宽16比特,深度为10的异步FIFO的设计,并要求给出空或满的指示信号。要求用Verilog HDL语言设计,并编写测试激励,以及用Modelsim进行功能仿真,验证设计正确性。10个16位的数据 (FIFO的宽度:也就是英文资料里常看到的THE WIDTH,它指的是FIFO一次读写操作的数据位,就像MCU有8位和16位,ARM 32位等等。FIFO的深度:THE DEEPTH,它指的是FIFO可以存储多少个N位的数据(如果宽度为N)。如一个8位的FIFO,若深度为8,它可以