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在FPGA中用costas环实现载波同步和数字下变频
- 在FPGA中用costas环实现载波同步和数字下变频，对于costas环的学习很有帮助
SDH_module
- SDH帧同步头的检测，并提取其中的语音信息的模块设计-SDH frame sync detection, and extract audio information module design
IPMSM_sensorless
- 无传感器永磁同步电机matlab仿真 pid自适应 已调的还可以-Sensorless permanent magnet synchronous motor adaptive pid matlab simulation has been adjusted, they can still
android-client
- syncML 协议使用的例子,手机和服务器同步通信-syncML
DSP PMSM
- DSP三相交流同步电机矢量控制(C程序_经典著).PMSM-DSP three-phase AC synchronous motor vector control (C program _ a classic).
Lorenz
- Lorenz混沌系统同步技术研究与仿真，基于PC法的混沌同步，基于线性状态反馈的混沌同步和基于观测器的混沌同步-Lorenz chaotic system synchronization technology research and simulation
WCF-to-achieve-data-syn-SQLServer
- 基于WCF实现SQLServer数据同步系统设计文档.pdf-WCF to achieve data synchronization SQLServer.rar
PMSM_Control_Using_MS320F2812
- TI提供的永磁同步电机矢量控制程序，一个完整的工程，采用TI公司的TMS320F2812作为核心处理器。-This document describes the "C" real control framework to demonstrate the PMSM demo implemented using CCS3.3.
mfc-multiThread
- MFC多线程编程实例，包括线程创建，线程间通信，线程同步等内容-MFC multi-threaded programming examples, including thread creation, communication between threads, thread synchronization etc.
syndetect
- 帧同步检测，verilog代码 是同步保护的经典范例-frame detection, verilog code
FTSP
- 无线传感器网络Tinyos环境下的时间同步算法FTSP实现代码-Wireless sensor networks Tinyos time environment to achieve code synchronization algorithm FTSP
PLLfpgapaper
- 实现数字锁相环的一篇论文，FPGA实现，用于位同步。-Paper digital PLL, FPGA implementation for bit synchronization.
chaos
- 蔡氏混沌同步，程序，调用十分完整，绝对好用。同机构同步系统-Chua' s chaotic synchronization, the program, call is complete, the absolute ease of use. Synchronization system with the agency
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序，已经仿真通过，可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
FileSystemWatcher200801141016
- Windows镜像服务器文件实时监控同步程序-Files Monitor
costas_loop
- 集中式插入式帧同步发的verilog源代码-concentrative inserted frame sync
timeServer
- linux下利用socket c语言编写的时间同步服务器和客户端，有流程图和注释，适合socket学习者~-under linux using socket c language time synchronization server and client, with flow charts and notes, suitable for socket learners ~
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
PMSM
- 基于Simulink的永磁同步电机的直接转矩控制的调速仿真，里面用S函数自建部分模块，加快了仿真速度。-Simulink-based permanent magnet synchronous motor direct torque control of the speed of simulation, which used self-built part of the S-function module to speed up the simulation speed.
FPGA_common_idea
- 本文讨论的四种常用FPGA/CPLD 设计思想与技巧：乒乓操作、串并转换、流水线操作、数据接口同步化，都是FPGA/CPLD 逻辑设计的内在规律的体现，合理地采用这些设计思想能在FPGA/CPLD 设计工作种取得事半功倍的效果。-This article discusses the four commonly used FPGA/CPLD design ideas and techniques: ping-pong operation, strings, and conversion, pipe