搜索资源列表
lab28
- 采用5级流水线MIPS微处理器设计，实现32位流水线的算数、逻辑、以为等指令-pipeline MIPS
PIPELINE
- （包含详细说明文档和简单汇编转机器码翻译器）五级流水线实现MIPS指令集（30条）含异常处理。结构采用多分支预测结构（基于历史的动态分支预测）-(Contains detailed documentation and compilation turn simple machine code translator) five pipelined MIPS instruction set (30) with exception handling. Structure using multi-bran
dot_product
- 实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构-Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure
Xie_3d
- 计算机图形学实验，三维输出流水线，从底层实现椭球体、正方体等三维图像的绘制。-Computer graphics experiment, three output lines, the underlying implementation ellipsoid, cube and other three-dimensional image rendering.
pcsystem
- 系统结构书本配套考试题，一定有用得到的地方，系统了解流水线等知识-System architecture supporting book exams, get some useful places to understand the pipeline system knowledge
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
pro3
- 电子科技大学计算机系统结构课程设计：加法乘法动态多功能流水线调度-University of Electronic Science and Technology Computer Architecture Course Design: Addition Multiplication versatile dynamic pipeline scheduling
pro2
- 电子科技大学计算机系统结构课程设计：加法乘法静态多功能流水线调度-University of Electronic Science and Technology Computer Architecture Course Design: Addition Multiplication static multifunction pipeline scheduling
pro1
- 电子科技大学计算机系统结构课程设计：模拟流水线指令调度-Design: Analog line instruction scheduling
Pipeline
- 用图形界面演示模型机的指令序列在5级流水线上的执行过程。使用高级语言Java，在Eclipse环境下开发流水线的仿真程序。实现针对任意的无相关模型机指令序列（包括数据前推、load前推并解决控制相关），能单步显示出每个时钟周期流水线上指令的执行情况，具体包括：时钟周期及编号、各级流水线寄存器的内容、各级流水线的控制信号。- Graphical interface demo model machine instruction sequence is d on five pipeline. U
Half
- 龙少炮灰单片机测试源码，配合龙少那个自制单片机使用,两级流水线-Long less cannon fodder microcontroller test code, with little dragon that homemade MCU, two lines
SRC
- 流水线CPU的verilog实现，包含id，if，ex，mem等部分的源码-an implementation of Pipelined CPU in verilog
dds_cordic
- 这是我自己编的一个基于流水线结构CORDIC算法实现DDS，32位的频率控制字的输入，CORDIC算法的迭代次数为15次。-This is my own DDS based on series of the pipelined CORDIC algorithm， a frequency control word：32 bit .The number of CORDIC iterations for the 15 time。
digital-logic
- 数字逻辑串并行流水线模拟，画时空图，给定一串字符流，模拟FIFO,LRU命中过程-Serial and parallel digital logic simulation pipeline, painting space-time diagram, given a character flow, analog FIFO, LRU hit processing
cpu
- cpu流水线代码，完整实现所有指令，包含top顶层文件的实现和仿真代码-cpu lines of code, complete implementation of all the instructions, including the implementation and simulation code top top level file
CPU
- 五级流水线.期末的project,写了很详细的注释，应该能看得懂了吧。-Five-stage pipeline. Closing the project, wrote a very detailed notes, should be able to understand it.
RISC-CPU
- 精简指令集 16位流水线CPU 可实现硬件模拟-16-bit pipelined RISC CPU hardware emulation can be achieved
flow-shop-problem
- 使用遗传算法来来解决求解置换流水线问题算法-matlab code for flowshop problem to use genetic algorithms
fifo_pipeline_booth_multiplier
- fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器，并且使用了流水线描述方式，本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
pipeline_lut_multiplier
- pipeline_lut_multiplier, 一个使用查找表实现的流水线乘法器，本程序使用verilog HDL language 语言编写-pipeline_lut_multiplier ，a multiplier based on look up tablets ,and it is programing in verilog language