搜索资源列表
VHDLpipeline
- 流水线实现圣经,可以大幅度提高系统时钟指标,可以提高编程水平-Pipeline to achieve the Bible, can greatly improve the system clock indicators, can increase the level of programming
mipscpudesign
- cpu设计实例mips。MIPSI指令集32位CPU(1)MiniCore设计实例全32位操作,32个32位通用寄存器,所有指令和地址全为32位 (2)静态流水线(3~5级) (3)Forwarding技术 (4)片内L1 Cache,指令、数据各4KByte,硬件初始化 (5)没有TLB,但系统控制协处理器(CP0)具有除页面映射外的全部功能 -cpu design example mips. MIPSI instruction set 32-bit CPU (1)
DES_IP
- 有效的改进3-DES算法的执行速度,采用了多级流水线技术,设计了一种高速的硬件结构,使得原来需要48个时钟周期才能完成的运算,现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中,大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed
liushuixian
- 功过模拟单功能流水线调度过程,掌握流水线技术,学会就算流水线的吞吐率,加速比,效率-Merits and demerits of single-function simulation pipeline for the activation process, master pipeline technology, even if the pipeline throughput Institute, speedup, efficiency
DES
- DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
pipeline
- 有关流水线的功能的西安交大的课件,讲的很详细,很好-about pipeline in pdf text
MIPS
- 带分支预测的MIPS流水线的verilog原代码。 详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
cpu16
- 实现一个16位CPU。该CPU使用精减指令集,是一个五段流水线的结构。包括取指令(IF)、读寄存器(RD)、运算器(ALU)、内存读写(MEM)和写回(WB)。-The realization of a 16-bit CPU. Streamline the use of the CPU instruction set is a structure of five lines. Including fetch (IF), register read (RD), arithmetic logic u
lunwen
- 潘明海 刘英哲 于维双 (论文) 中文摘要: 本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法,简化了部分积符号扩展,使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计,并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Mingha
6_seg_cpu
- 我写的6段流水线cpu,供大家参考。里面包括了alu memory topcpu等模块-I wrote a six-stage pipeline CPU, for your reference
if
- 5级流水线的取址阶段,自己编的,可以用-Five pipeline stages to take the site himself compiled, you can use
id
- 用vhdl写的流水线译码阶段,绝对好用-Written in line with the vhdl decoding stage, absolutely easy to use
we
- 用VHDL写的5级流水线的回写阶段,绝对好用-Using VHDL written five stage pipeline write-back, absolutely easy to use
WinDLX
- DLX模拟器用软件模拟DLX流水线的工作过程,可以灵活、方便地设置参数、控制执行和统计数据,并提供了直观的窗口显示。-DLX simulator software simulation of DLX pipeline work process can be flexible and easy to set up parameters, control, execution and statistical data, and provides an intuitive window display
MIPS
- MIPS-lite Simulator 流水线模拟器实现-MIPS-lite Simulator pipeline simulator to achieve
cpudesheji
- CPUname是RISC处理器,采用普林斯顿体系结构,CPU与数据存储器间的通信使用Load/Store指令实现,数据存储采取统一的32位字长格式,32位定长指令,地址指令格式。使用专用数据通路结构,四级流水线,分为取指及译码,取数,运算,回写四步,拥有相关专用通路以解决数据相关问题,对跳转指令应用分支预测技术,使其不影响流水。-CPUname is a RISC processor, using the Princeton architecture, CPU and data memory,
LAB21
- EDA基础_综合实验篇__实验二十一 采用流水线技术设计高速数字相关器-EDA based on comprehensive test papers _ __ pipelined technology experiment 21 high-speed digital correlator design
DLX
- 模拟的汇编器,可对汇编代码进行汇编,然后模拟流水线执行汇编指令-Simulated assembler, assembly code can be compiled, and then simulate pipeline execution assembly instructions
ClientCim
- linux环境开发,应用于生产流水线流程监控及管理,适应于大型厂房流水线,非常好的产品代码-linux environment, development, production lines used in process monitoring and management, adapted to large-scale factory production line, very good product code
80870991pipeline
- 计算机体系结构中关于通用5级流水线的模拟实现程序-Computer architecture in general 5-stage pipeline on the implementation process simulation