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- java--工作流--在网络技术和移动电话严重渗入社会生活各个层面的今天,传统的电信号线业务面临着巨大的压力和挑战,为了能更好地生存和拓宽他的业务,迫切需要及时变革,而基于工作流的方案则是一个很重要的方向。基于Web技术的固定电话装机系统可以借助于遍布全球的Internet进行,使得固定电话业务以流水线的工作原理和效率来实现,并以统一的数据来联系各个部门,减少-java- the workflow- in network technology and a serious infiltratio
yibin
- 宜宾家具厂流水线控制程序,日本三菱PLC编写。-Furniture Factory Yibin line control procedures, the preparation of Japan' s Mitsubishi PLC.
adder
- 采用加法树流水线乘法构造八位乘法器,并分析设计的性能和结果在时钟节拍上落后的影响因素。 -Multiplication using adder tree structure line 8 multiplier, the design and analysis of the results of the performance and beat the clock on the impact of the factors behind.
erweiDCT
- 用 FPGA实现了二维离散余弦变换和逆变换,结构设计采用行列分解法,乘法器采用移位求和的方法实现,并且采用流水线结构设计,提高处理核的性能-Using FPGA to achieve the two-dimensional discrete cosine transform and inverse transform, the structural design of the use of the ranks of decomposition, the sum of multipliers us
HurricaneLamp
- 此设计为走马灯试验,芯片为AT89C51,16个发光二极管流水线依次点亮。-This lantern is designed to test chips for the AT89C51, 16 LEDs light lines followed.
FPGA_design_of_a_pipelined_CPU
- 基于FPGA流水线CPU控制器的设计与实现:在FPGA上设计并实现了一种具有MIPS风格的CPU硬布线控制器。-FPGA design of a pipelined CPU:a hard-wiring CPU controller with a MIPS-style is designed in FPGA.
Realization_of_8051_microcontroller_core_based_on_
- 基于流水线架构8051微控制器内核的实现,上海交大的一篇硕士毕业论文,很有参考价值-Realization of 8051 microcontroller core based on pipelined architecture, a master s thesis of Shanghai Jiaotong University, is valuable for reference
video
- 数字视频信号流水线处理的4个实例: 实例1:产生蓝屏 实例2:产生彩色条测试图像 实例3:叠加移动的物体 实例4:叠加动态视频-Four examples of digital video pipeline
Simulation_modeling_of_the_solar_system
- 模拟太阳系的建模(几何流水线的实现),自己做的^_^-Simulation modeling of the solar system (the geometric realization of pipeline)
H264
- h.264(verilog HDL) 这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
FPGAANDFILTER
- FIR数字滤波器设计FPGA实现的研究。流水线技术在文中得到了应用,提高了数据处理的速度-FIR digital filter design FPGA realization of research. Lines in the text has been applied to improve the speed of data processing
UartAssist
- 在数字信号处理领域用的较多的是DSP和FPGA。DSP的优势源于多数信号处理算法的乘-累加运算都是非常密集的。FPGA通过多极流水线架构也能够用来实现MAC单元,并且FPGA技术可以通过一个芯片上的多级MAC单元来提供更多的带宽,速度可以比数字信号处理芯片快,并且功耗较低。CORD IC算法完全由移位和加法操作完成,因此利用FPGA可以实现更高的运算速度。采用流水线结构在FPGA上实现基于CORD IC的对数变换,可以达到80MHz的处理速度。
ThreeDimensionalLine
- 利用VC++来实现三位流水线的绘图实现,算法很好-Using VC++ to achieve the realization of the three lines of the drawing, a good algorithm,
Radiofrequencycardreader
- 射频读卡器方案 该方案采用Silicon Lab 公司超低功耗SOC 型单片机C8051F31x,流水线指令 结构,70 指令执行时间为一个或两个系统时钟周期,速度可达25MIPS 灵活的 时钟源-Radio frequency card reader program used the program Silicon Lab company SOC-based single-chip ultra-low power C8051F31x, command line structure,
FIR_Direkt_BAB_P
- VHDL编写的代码。采用流水线方法实现的FIR滤波器。22阶。Fa=48kHz, Fc=10KHz。可用ModeSim仿真并FPGA实现-Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA
two_d_dct_serial
- 二维DCT变换,采用查找表的方法实现算法,分别通过列变换,再通过行变换,通过加法器乘法器以及流水线技术得出更快的结果!-two-dimention DCTtransform,the algorithm was implemented by look up table,via row trasforming and colum trasforming respectively
longson-2e-pdf
- 龙芯2E处理器是一款实现64位MIPS III指令集的通用RISC处理器。龙芯2E的指令流水线每个时钟周期取四条指令进行译码,并且动态地发射到五个全流水的功能部件中。虽然指令在保证依赖关系的前提下进行乱序执行,但是指令的提交还是按照程序原来的顺序,以保证精确中断和访存顺序执行。-Godson-2E processor is a realization of a 64-bit MIPS III instruction set of general-purpose RISC processor. G
file_encryption
- AES分组加密算法做的文件加解密演示, 采用多线程流水线方式对文件进行 读->加密/解密->写 操作.-AES block cipher algorithm for encryption and decryption so the paper presentations, the use of multi-threaded pipelined read on paper-> encryption/decryption-> write operation.
5_lined_cpu
- 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
CPU_verilog
- 一个4级流水线CPU的verilog代码,供参考学习使用,有些语句不能综合,可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.