搜索资源列表
pipeline_streamlined_divider
- pipeline_streamlined_divider, 一个流水线的除法器，使用Verilog HDL语言编写-pipeline_streamlined_divider， a divider using pipeline technology in verilog HDL language
ppv2
- pipeline流水线用MIPS实现，用的是verilog。解决流水线的各种冲突。-pipeline pipeline with MIPS implementation, using verilog. Resolve conflicts pipeline.
DC-Adder_Array
- 要求采用快速进位链（Look Ahead）设计一个21位加法器； 2) 采用结构化的设计方法，所有加法器均采用步骤1）的21位加法器； 3) 在加法器阵列中加入流水线结构（Pipelinc），输入连续送数，输出连续出结果，流水线填满后每拍输出一个结果； -1) requires the use of fast carry chain (Look Ahead) design a 21-bit adder 2) the use of structured design metho
pipe_mul
- 移位加乘法器的实现；移位加乘法器的流水线结构的实现。代码清晰明了。-multiply verilog RTL；pipelin multiply verilog RTL；good coding stytle
Cordic-arithmetic-pipeline
- FPGA实现基于Cordic算法的流水线结构设计，相关verilog语言代码-FPGA to realize the Cordic code
add48
- add48 是6级流水线方式实现加法-add48 are six ways pipelined adder
Lab
- 硬件编程实现处理器。包括ALU、编译器、单周期处理器、流水线处理器等多个部分。-Processor by VDHL
Proj2_final
- 2 4 8级流水线乘法器 以及 除法器 包括makefile 和 tcl 比较详细-248 stage pipeline multiplier and divider includes more detailed makefile and tcl
123
- 一个自己写的！ 自己拿去改改，非常不错！让借贷宝赚钱成为一条流水线，不断营销你的ID！ 你懂得！-Write their own! Own take to change to change, very good! Let borrowing money has become a pipeline treasure, constantly marketing your ID! you know!
cpu
- vhdl实现处理器基本功能，不包括流水线-VHDL to achieve the basic functions of the processor
PPE
- 开方，求倒数，开方的倒数三种快速运算。采用流水线结构，latency为23周期。-this unit can realize three functions,that is sqart,reciprocal and reciprocal of sqart. adopt fast algorithm and pipeline architecture. the latency is 23 clock cycles.
cordic
- verilog编写的数字信号发生器NCO用CORDIC方法实现产生sin cos信号，流水线结构，简单实用。-verilog prepared by the digital signal generator NCO using CORDIC method implementation generate sin cos signal, pipelined architecture, simple and practical。
ccccc
- 关于车间调度的一个主程序，是关于服装生产流水线工序编排的主程序-A main program on the shop scheduling
02MATLAB
- 流水线车间生产调度的遗传算法MATLAB源代码 n个任务在流水线上进行m个阶段的加工，每一阶段至少有一台机器且至少有一个阶段存在多台机器，并且同一阶段上各机器的处理性能相同，在每一阶段各任务均要完成一道工序，各任务的每道工序可以在相应阶段上的任意一台机器上加工，已知任务各道工序的处理时间，要求确定所有任务的排序以及每一阶段上机器的分配情况，使得调度指标(一般求Makespan)最小-Line workshop production scheduling genetic algorithm M
liushui
- 本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写-This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language
pipline_lms_and_rls_verilog
- 流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。-The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.
rfidtest
- RFID流水线测试，运用控制变量的方法，将影响电子标签的客观因素逐一进行测试、对比。定性的分析和研究在各种客观条件下，RFID读写器对电子标签在流水线系统中的读取率的影响和流水线中读写器的布置指标。-RFID pipeline test, using the control variable method, the objective factors will affect the electronic tag of each test, comparison. Qualitative anal
CPU_Project_board
- CPU 5级流水线实现（加hazard处理与板级验证，板级验证带有按键消抖）-5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce)
Barcode
- 条码出入库实例，VB+SQL可用流水线自动扫码入库，也可打包入库-Barcode out of storage instances, VB+ SQL available line automatically scan code storage, can also be packaged storage
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction