搜索资源列表
motor
- 两个机械手电机控制系统,适用流水线自动化制造,stc12A5CPWM控制步进电机-Two robotic motor control systems for automated manufacturing lines, stc12A5CPWM stepper motor control
pipeline
- 流水线部分模块,流水线寄存器的实现,ex级-Assembly line part of the module, pipeline register
Release
- socket流水线服务器,该服务器自动连接各个客户端-socket TCP/IP
BoardTesting
- 三条流水线上每一块板卡进行检测来确定电路板上的各个元件是否摆放正确,在每一条流水线上放置一台摄像机,并将电路板的图片发送到同一计算机上,计算机通过检测程序来判断电路板是否安装正确-Each board for testing on three lines to identify the various components on the board are correctly placed, placed a video camera on every line, and the image i
IDCT
- HEVC是正在研发的新一代视频编码标准。 本文面向HDTV应用,设计兼容HEVC标准的两位整数IDCT电路, 通过对IDCT的特点进行分析,完成了电路的架构设计, 采用较为节省面积的做法和流水线结构,并进行VerilogHDL代码设计-High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architect
mips
- 基于mips架构的五级流水线硬件实现。使用verilog-Based on the five-stage pipeline hardware architecture mips
sbox_pprm
- PPRM结构SM4算法S盒C语言实现,该结构逻辑简单,灵活性大,非常适用于流水线结构- PPRM structure S box of SM4 algorithm is realized in C language. The logic structure is simple , flexible, ideal for the pipelined structure .
three-pipelined-SM4
- 单轮三级流水结构SM4算法,该结构电路比传统流水线具有明显的资源消耗优势,而且比单轮迭代SM4算法具有更快加解密运算速度,实现更大的吞吐率。-Single round three pipeline structure SM4 algorithms, the circuit structure than conventional lines, with obvious advantages of resource consumption, and more than a single iterat
Code1
- 拥有提前判断,和假设分支条件不满足的流水线CPU- Pipeline CPU with forwarding and predict-not-taken
CPU-
- 五级流水线CPU实现(带Hazard),还没来得及实现Cache求高人指教-pipeline CPU with Hazard
windlx
- 计算机体系结构windlx流水线实验 输入位数相同的两个整数,逆序输出同位上相同的数 -Computer architecture windlx pipeline experiment Enter two integers the same number, the same number of reverse output parity
variable-frequency-speed-regulation
- 文章主要介绍了利用单片机和变频器之间的通信实现多台电机在自动化生产流水线中的同步控制。描述了控制的硬件配置和软件编程。采用A T89S51 单片机为控制器、国产佳灵J P6C 型变频器为执行器来控制电机,在实际应用中能够很好地满足生产的需要。-This paper mainly introduces the realization of synchronous control of multi motor in automatic production line by using the com
Micromouse_Pixy
- 视觉追踪 Pixy ARM控制工程,其工程可用于武器系统的开发,工业中生产流水线的自动跟踪上货系统。-Visual tracking Pixy ARM control engineering
multier
- 流水线高速并行乘法器,流水线设计,并行加法计算-High-speed parallel pipelined multiplier
32bit_add_exercise
- 32位全加器,另有一个采用流水线的版本,是基于verilog语言的,很实用,希望对大家有所帮助-32-bit full adder, while a pipelined version,code is based on verilog language, it is practical, we hope to help
gear-detection-VS2010
- 齿轮检测 用于流水线上的基于摄像头的齿轮检测-gear detection based on camera gear detection
pcpu_handle_mem
- Verilog实现五级流水线CPU,hazard以及时序功能已经实现。-Realize five-stage pipeline CPU
code
- 汇编语言16位五级流水线,已实现Hazard处理-Assembly Language 16 five-stage pipeline, processing has been implemented Hazard
CRC-generator
- 提出了一种32位并行和高度流水线的循环冗余码(CRC)发生器。 该设计可以处理5个不同的通道,每个输入速率为2Gbps(总输出吞吐量为5x4Gbps)。 生成的CRC与32位以太网标准兼容。 该电路已经在0.35Micron标准CMOS工艺中使用标准单元实现,其使用Galois Fields的特性,并且被认为是“自由的”IP。-A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is
changedirection
- 这是一个金库流水线上的调相设备软件,使用单片机stc12c5a60s2,当包扎好的钱币进入检测范围时,设备首先确定奇数或偶数的圈数,然后当钱币数为奇数时,调整钱币的方向,使整个纸币整齐,易于识别和计数,然后进入下一个过程,捆绑包装。-This is a vault line on the phase modulation equipment software, the use of single-chip stc12c5a60s2, when the bandaged money into th