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fifo
- 模拟操作系统进程调用的一个fifo先进先出的程序-Simulate the process of the operating system calls the program a fifo FIFO
fifo
- 基于verilog的异步fifo设计，仿真效果良好-asynchronous fifo based on zhe verilog language
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
Verilog
- 异步fifo的经典写法，使用verilog语言编写的。-Asynchronous fifo' s classic formulation, using verilog language.
UART_spec
- a UART model with FIFO buffer, design with verilog
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
generic_fifos
- Generic FIFO for use with both xilinx and altera
program
- 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the fi
CY7C68013FPGA
- USB控制芯片cy7c68013与FPGA通过slave fifo方式通信，块传输数据-USB controller chip and FPGA cy7c68013 way communication through the slave fifo, block data transfer
DSP_2812_SCI_232
- DSP2812串口通信编程，利用FIFO中断接收数据以及利用查询方式发送数据-TMS320F2812SCI code
Change
- 用JAVA实现操作系统的页面置换 其中包括 最佳置换算法(Optimal)、先进先出算法（First-in, First-out） 、最近最久不用的页面置换算法（LeastRecently Used Replacement）三种算法的实现-JAVA realization of the operating system with replacement pages including the best replacement algorithm (Optimal), FIFO algorit
altera_fifo
- altera 公司的 FIFO 文档，这是设计同步或异步FIFO的重要文档-altera s FIFO document
USB_Interface
- verilog USB USB的slave fifo的控制-verilog USB
ADS
- ads8365的高速采集程序，采样率100kbps,6通道同步采样，采用FIFO模式-ads8365 high-speed acquisition procedures, sampling rate of 100kbps, 6-Channel Simultaneous Sampling, using FIFO mode
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
cache
- （1）FIFO：First In First Out，先进先出 （2）LRU：Least Recently Used，最近最少使用 （3）LFU：Least Frequently Used，最不经常使用-（1）FIFO：First In First Out （2）LRU：Least Recently Used （3）LFU：Least Frequently Used
13
- para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)