搜索资源列表
asyn_fifo_bk
- 该verilog代码位手动编写的异步fifo。-This code is manually generated asychronous fifo.
prj_5
- FIFO Using MyFIFO_Block_Memory_v7_1 with verilog code
FIFOverilog
- 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
verilog_fifo.tar
- Verilog FIFO model independent
61EDA_C2212
- 红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序-Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO
UART_FIFO
- Verilog编写的串口配合FIFO的代码，对大家学习串口和FIFO有一定帮助-Verilog prepared with FIFO serial code, we learn the serial port and FIFO have some help
syn_fifo
- 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
myuart
- 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and
exercise3
- 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modul
VGA800
- 本代码用verilog语言，配合quartus里自带的fifo来简单实现vga显示屏的操作，重点在于弄清楚时序。代码中被注释的部分也可以用于彩色条纹的测试。-The code to use verilog language, with quartus in fifo comes to simply achieve vga screen operation, with emphasis on clear timing. The code portion of the notes can be te
ht_fifo
- fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
20131010-code
- fx2lp 68013 xilinx XC3s400 实现slave fifo通讯，包括68013的固件以及fpga的代码（verilog）。摸了好久才调试通过的，特共享出来解救苍生！-fx2lp 68013 xilinx XC3s400 slave fifo
async_pulse
- asynchronous fifo with pulse input write by verilog code
synchoronous_FIFO(jianban)
- 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
FIFO64
- FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
fifo_datapath
- verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
vga_pannel_design
- verilog代码写的控制vga显示的实例，利用状态机进行描述，很好的参考例子-verilog language write serial fifo instance, because the serial port speed is relatively slow, a lot of the interface will use fifo buffer
I2S
- 本代码提供一种音频I2S读取数据的verilog代码，并且向fifo写入-This code provides an I2S audio data is read verilog code, and write to the fifo
fifo2
- 异步fifo 先进先出 用于缓冲数据，用verilog HDL所写，在quartus II中测试通过，modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by