搜索资源列表
UART
- 已经过调试成功的fpga串口模块，verilog编写-Has been successful commissioning of fpga serial module, verilog write
communicate
- FPGA 串口通信（1位起始位，8位数据位，无奇偶校验位和握手位）-FPGA based serial communication
UART01
- 可靠的FPGA串口收发程序，用Verilog编写，可以自行调整波特率！-Reliable FPGA serial transceiver procedures, with Verilog prepared to adjust the baud rate themselves!
action_vip_uart
- FPGA串口使用程序，通过调试验证，直接调用即可，方便使用-FPGA UART
Serial
- FPGA 串口通信方法1 亲测能用，来自小桥流水的博客-FPGA Serial communication http://blog.sina.com.cn/s/blog_52e8baa40100saen.html
uartverilog
- FPGA串口通信-来自小梅哥，能快速发送，超长发送没有误码-FPGA Serial communication
uart_txrx
- fpga 串口发送与接收VHDL硬件语言实现。附有仿真测试程序。-fpga serial port to send and receive VHDL hardware language. With simulation testing program.
uart
- 用Verilog HDL，实现的FPGA串口调试程序，已经在硬件上调试成功-With Verilog HDL, FPGA serial debugger implemented in hardware debugging has been successful
verilog_UART
- verilog语言 FPGA 串口收发模块，既可以接收也可以发送，可以自行更改波特率-Verilog language FPGA serial transceiver module, I can receive can send also to change the baud rate
receive_uart
- fpga串口通信，接收模块程序.verilog语言编写-fpga serial communication, receiving module program
reciever
- 利用vhdl语言编写的FPGA串口接受程序-Vhdl language use FPGA Serial acceptance procedure
uart
- verilog 编写的FPGA串口报文收发程序，带奇偶校验位，并含有DS18B20温度传感器驱动程序，可以自行设置波特率.-verilog prepared by the FPGA serial transceiver procedures packets with parity, and contains a temperature sensor DS18B20 driver, you can set the baud rate yourself.
FPGA-auto-car-and-arm
- VHDL Verilog编写，实现无线串口通信遥控4自由度机械臂和车身行动驱动。串口命令格式和舵机参数可根据实际需要自行调整-Verilog VHDL prepared to achieve a wireless serial communication remote control 4 degrees of freedom manipulator and body action. Serial command format and actuator parameters can be adju
uart
- FPGA 串口发送程序，基于verilog HDL，对于串口调试还是很有帮助的哦。-FPGA serial transmission program, based on verilog HDL, or helpful for debugging serial oh.
FPGA-and-TDC-GPl
- 对高精度短距离测量的需要，以现场可编程门阵列(FPGA)为控制核心，采用高精度时间数字 转换芯片TDC—GPl和433 MHz超再生射频发射、接收模块，设计了一种高精度的到达时间差(TDOA)测距 系统。该测距系统由发射节点与接收节点组成，其中发射节点由FPGA控制433 MHz超再生射频信号与 超声波信号的同步实时发射；接收节点将接收的射频信号与超声波信号，经过TDC．GPl进行TDOA测量， 并由FPGA完成对TDC—GPl的测量参数配置、测量结果读取及串口上传到上位机。该测
source
- FPGA串口，verilog HDL串口收发程序-FPGA serial, verilog HDL serial transceiver procedures
Uart_Loop
- FPGA串口的模块和一些相关的pdf资料和串口调试助手-uart module for fpga with pdf data
UART_TX
- FPGA串口发送测试程序，包含按键模块，串口发送模块，和串口模块的testbench文件-FPGA serial port test program, including testbench file button module, serial sending module, and the module' s serial
FPGA-for-UART-source-code
- 针对UART接口通信FPGA的Verilog源代码，主要包括串口读和串口写个模块-Verilog source code for UART interface communication FPGA, including serial read and serial write module
UART_noFIFO
- FPGA串口调试程序，不含FIFOIP核-FPGA u4E32 u53E3 u8C03 u8BD5 u7A0B u5E8F uFF0C u4E0D u542BFIFOIP u6838