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Sim_Fast_Tanner
- matlab to ise change code
StopWatch
- This a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.-This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
xilinx_ise
- Xilinx ISE 14.4 Lincense，实测可用-Xilinx ISE 14.4 Lincense, actual available
Counter
- Counter in VHDL using Xilinx ISE
fft
- FPGA实现FFT算法的源代码及工程文件，此工程为ISE工程项目。有详细的说明，可以运行。-FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.
alu
- 可以实现十六种算术运算和逻辑运算的VHDL代码哦，ISE上编译仿真可以运行-Can achieve sixteen kinds of arithmetic and logic operations of the VHDL code Oh, ISE compiled simulation can be run on
fsm
- 检测连续3个1的状态机的VHDL代码，输入11111则输出00111，ISE可以编译仿真，运行-Detecting consecutive three one state machine VHDL code, enter 11111 Output 00111, ISE can compile simulation run
lablab2
- 实现四位串入串出的移位寄存器，其实就是四个D触发器相连的VHDL代码，ISE可以运行-Achieve four string into the string out of the shift register, in fact, four D flip-flop connected to the VHDL code, ISE can run
Signal3
- ISE设计的三角波发生器VHDL实现及报告-ISE Design of the triangular wave generator VHDL implementation and reporting.
Study-ISE
- Xilinx 的ISE10.1软件 开发学习教程-ISE10.1 the Xilinx Software Development tutorials
18B20
- verilog 写的18b20温度采集程序，并通过串品模块送出-verilog 18b20 uart ise
key
- PS2键盘协议代码 verilog，可以在ISE上跑，约束条件：NET"F50M" LOC="B8" NET"ps2_clk" LOC="R12" NET"ps2_data" LOC="P11" NET"rst" LOC="H13" NET"seg[6]" LOC="L18" NET"seg[5]" LOC="F18" NET"seg[4]" LOC="D17" NET"seg[3]" LOC="D16" NET"seg[2]" LOC="G14"
61IC_S4182
- 基于FPGA设计工具Xilinx ISE 编写的程序代码-Xilinx ISE FPGA-based design tools to write program code
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
CPU_project
- CPU设计与实践实验源码，工程文件 ise。VHDL代码 可直接运行-cpu project
Experiment04
- 浮点数的除法器的Verilog 源代码，使用Quartus II开发环境编写，塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
moore
- 状态机 基于xilinx ise硬件描述语言-moore VHDL
counter4
- 计数器 基于xilinx ise硬件描述语言-counter VHDL
con_ram_success
- 利用ise中的ip核，实现在任意地址存储和读取数据-In the ise， using ip core, arbitrary address storing and reading data
rom123
- 利用ise中的ip核，实现rom的基本功能，通过此程序，学习掌握rom的工作原理及特性-In ise the， using ip core, implement basic functions of the rom and learning to master the working principle and characteristics of the rom