搜索资源列表
lab2
- 熟悉XUPV2P实验开发平台。熟悉掌握Verilog HDL语言并能用其建立基本 的逻辑部件在Xilinx ISE平台进行输入、编辑、调试、仿真-Familiar XUPV2P experimental development platform. Familiar with Verilog HDL language and be able to establish its basic logical components in Xilinx ISE platform for entering
add
- 北京邮电大学VHDL课程作业，基于xilince ISE试验箱开发的，可以做简单的半加器加法-Beijing University of Posts and VHDL course work, based xilince ISE chamber developed, can do simple addition of half-adder
rili
- 北邮的大作业，基于ISE试验箱编程的万年历，LCD数码管显示，可以开关控制，测试成功-Great job BUPT, based on the ISE chamber programming calendar, LCD digital display, you can switch control, the test is successful
Washing_VHDL-v1
- 一个全自动洗衣机，三个状态及显示。 开发环境为xilinx ise-a autowasher with 3 states
two_ASK
- ask调制在xilinx ise各个版本下的源码和仿真源码-ask the modulation source in the xilinxise
FPGA-logic-designer-test
- 该文件包含了FPGA逻辑设计实验的相关代码，提供了ISE平台下可直接运行的代码-This file contains the FPGA logic design experiments related code, provides the code can be run directly under the ISE platform
rs(63-45)
- 用VHDL实现的RS（63,45）编码器，已经用ISE和questasim编译仿真通过。对45个信息位进行编码。-VHDL implementation of the RS (63,45) encoder has been compiled with the ISE and questasim through simulation. Of 45 information bits are encoded.
Ecar
- 基于FPGA的一个小游戏，在VGA上实现赛车游戏,开发版型号为ANVYL燧石，在Xilinx ISE环境下编译-An FPGA-based games, racing games on the realization VGA, Developer Edition model ANVYL flint, compiled under Xilinx ISE environment
1540000000000031952_taxi
- 一个基于FPGA使用VHDL语言编译的出租车计价器，在Xilinx ISE环境下编译-An FPGA using VHDL language compiler taxi meter, compiled under Xilinx ISE environment
TouchPad
- 一个触摸屏打地鼠小游戏 ，利用VHDL实现，在Xilinx ISE环境下编译。-A touch-screen play hamster game, using the VHDL implementation, compiled under Xilinx ISE environment.
lab10.2
- 4bit Adder in ISE 14.7
vga_stripes_top
- VGA彩条显示,分辨率800*600,使用Verilog显示间隔可设置的红绿条纹,使用工具为xlinx ise.-VGA color display with a resolution of 800* 600, the use of red and green stripes Verilog display interval can be set using tools xlinx ise.
Bin2BCD_project
- binery 2 BCD decoderwith xilinx ISE synthesis and place and route
a_sum_b
- this is a 2 bit adder for xilinx with ise 9.2
divideer_2
- this is a 2 bit divider for xilinx whit ise 9.2
ram_4_4
- this is a 2 bit ram for xilinx whit ise 9.2
xx_float_add
- 32bit浮点数加法。只实现了两个正数的相加，通过modelsim仿真。开发环境为 Xilinx ISE。-32bit floating point adder. Only realized the sum of two positive numbers through modelsim simulation. Development environment for Xilinx ISE.
Arbitrary-_odd_-frequency_VHDL_code
- 任意奇数分频的VHDL代码和testbench测试VHDL代码，经过ISE的ISim仿真工具测试，模块功能准确有效，特此分享！-Arbitrary odd frequency of VHDL code and test VHDL testbench code, after the ISE ISim simulation tool to test module functions accurately and effectively, would like to share!
CX40_Code
- 某公司的驱动TFT LCD的测试代码,使用VHDL，ISE环境-A company' s drive TFT LCD test code
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language