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add_success
- 在ise中，实现两个ip核分别做加数和被加数，并将结果存在另一个ip-In ise, the realization of two summand and ip nuclear summand were done, and the results there is another ip
ram_test
- ISE中双端口不同位宽ram的数据存储，包括testbench-veirlog ram FPGA
paobiao
- ISE仿真平台下建立的用verilog语言实现的简易数字跑表工程-Simple digital stopwatch works with verilog language of the establishment of the ISE simulation platform
comptage-sur-un-afficheur33
- matbal file for xilinx design ISE ...compteur, bascule-matbal file for xilinx design ISE ...compteur, bascule....
VGA-a353
- PROGRAM FILE ...... XILINX ISE DESIGN....2014
1245_COR
- simulink of mobile robot vhdl and ise matlab progra-simulink of mobile robot vhdl and ise matlab programm
ExamTechAss2009
- un controller pi par le langage VHDL xilinx ise design 13.2
TechAss-2006
- un controller pi par le langage VHDL xilinx ise design 13.2
simulink-QPSK
- 对QPSK解调系统完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。 matlab版本：2007a-Perfect for QPSK demodulation system modeling, which by changing the symbol rate and carrier frequency, and then calculate t
simulink-8PSK
- 对8PSK完美建模，其中通过改变码元速率和载波频率，再计算相应的环路滤波器的参数，即可实现多种QPSK模型的解调，且该模型可通过SYSTEM generator进行量化，从而生成ISE能直接使用的HDL代码。-Perfect modeling of 8PSK, wherein by changing the symbol rate and carrier frequency, and calculate the corresponding parameters of the loop filte
Greedy_snake
- 利用Xilinx ISE平台在FPGA实验板和VGA显示屏上完成简单的贪吃蛇游戏-Use Xilinx ISE platform to complete a simple Snake game on FPGA experimental board and VGA display
counter60
- ise环境下用hdl语言编写的60进制计数器，已调试通过-60 binary counter
Verilog
- 利用verilog 语言在ISE上运行仿真，利用BASY2开发板运行实现。-BASY2 engineered for ISE
gate4
- 运用verilog 语言编程，实现4输入逻辑门设计，利用ISE软件仿真，把程序下载到BASY2开发板上运行实现。-BASY2 engineered for ISE
lab3_clock_20120520
- 基于ise的多功能数字钟设计。适用于basys2开发板-Ise-based multi-functional digital clock design
ml605_PCIe_Gen1_x8_rdf0008_13.2_c
- 基于ML605开发板生成的x8 PCIE验证程序，可在ISE 13.2上正常运行，用户可根据自身需求进行修改-ML605 development board based on the generated x8 PCIE verification process can be run properly in ISE 13.2, the user can modify according to their needs
16QAM
- 使用verilog编写的16QAM调制解调代码，可用于quartus和ISE，因为不包含FIR，只能用于仿真，不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
adc0809
- ADC0809转换器的verilog版本,运用在ISE上，直接可用（注意没有考虑频道问题），结果显示在数码管里（十进制）-Verilog version ADC0809 converters, used in the ISE, directly available (note does not consider channel problems), the results are displayed in the digital tube (decimal)
ISE_Modelsim-
- ISE与modelsim开发环境进行联机，设置经验的总结-ISE and modelsim online development environment, set and experience in
EDK_IP_ISE
- 最近忙一个EDK的小工程，自己定义个用Create or Import Peripheral 定义了IP，在里面要用到ISE的IP.困扰了一段时间！经过群里、论坛上一些朋友的帮助 终于OK了-EDK little busy recently a project with their own definition of a Create or Import Peripheral define the IP, in which to use the ISE IP. Troubled for some