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Lab4_hex7seg
- 7段译码器的设计与实现.nexy3开发板。通过使用ISE软件进行7段译码器的设计与实现。-Xilinx ISE 12.3.nexy3
Lab5_x7seg
- 7段显示管的设计与实现.nexy3开发板。在2个7段显示管上显示一个2位的十六进制数，本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3.
Lab6_decode38a
- 3-8译码器的设计与实现.3-8译码器的真值表，本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3
Digital_Logic_Design
- 基于Xilinx ISE入门材料。包含数字电路入门程序。应用于NEXY3开发板。-ISE entry materials based on Xilinx. Contains digital circuit entry procedures. Applied to the NEXY3 development board.
S16_ADC
- 用Verilog HDL语言编写的AD转换器，可以再Xilinx芯片实现，用ISE软件环境下开发-Using Verilog HDL language AD converter, you can then Xilinx chip, with the ISE software development environment
LEDs
- ISE实现流水灯，并使用开关控制流水灯走动速度，对于硬IP核初学者很有帮助，代码绝对在ISE14.6上做过验证。-ISE achieve water lights, and use the switch to control light water walking speed, hard IP core for beginners, code validation is absolutely done on ISE14.6.
I2C
- I2C总线控制器的VHDL代码、ISE工程文件、ModelSim仿真环境等-I2C bus controller VHDL code, ISE project file, ModelSim simulation environment
radix_4_fft
- ISE 实现基4的16点fft~整个工程和源码-fft based-radix_4 realized
yima
- Verilog语言描述38译码器功能，适用于ISE或者quartus软件-Verilog language descr iption 38 decoder function for ISE or quartus software
or1200_alu
- 该代码为OR1200 CPU中ALU部件，在ISE中综合成功，希望能为对HDL感兴趣的朋友提供帮助。-The code for the OR1200 CPU in ALU components in a comprehensive success in the ISE, hoping to interest in HDL as a friend to help.
cordic
- ise下用verilog实现的cordic算法的实现程序-ise under cordic algorithm verilog achieved with implementation of the program
vhdlcodes10
- FPGA/CPLD集成开发环境ise的使用详解 示例代码10-FPGA/CPLD integrated development environment IDE ise the example code 10
vhdlcodes11
- FPGA/CPLD集成开发环境ise的使用详解 示例代码-FPGA/CPLD integrated development environment IDE ise the example code
vhdlcodes9
- FPGA/CPLD集成开发环境ise的使用详解 示例代码9-FPGA/CPLD Integrated Development Environment ise Comments on the use of code examples 9
run_led
- Xilinx FPGA, ISE工程文件，Verilog语言实现流水灯，设计了分频器，可精确到点亮时间为一秒，可控制流水灯左右移位方向-Xilinx FPGA, ISE project file, Verilog language water lights, designed divider, accurate to one second light time, you can control the direction of light water left shift
CAN_IP_2014-4-20
- CAN IP核的详细实现 直接运用 可以用ISE直接打开-CAN IP USE
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
arm_clear
- 功能为数组清零，是用来用linux系统生成汇编代码，再反汇编编译链接成.o文件，之后在ISE上看仿真波形图的-Features an array cleared, is used to generate assembly code using linux system, then disassemble compiled and linked into. O files, after watching the simulation waveform diagram of ISE
monitoringV5
- 文件的FPGA是基于Xilinx ISE写的，所用开发板为zedboard7020 484系列，完成的功能为：读取XADC里的温度，VCC，并存储到RAM中，通过流水灯实现翻看，读取等功能.-Document is based on Xilinx ISE FPGA wrote, the use of development board for zedboard7020 484 series, completed functions: reading XADC in temperature, VC