搜索资源列表
vhdl-2
- UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
VHDL语言的UART串行接口芯片程序
- VHDL语言的UART串行接口芯片程序
UART.使用FPGA的FIFO，状态机
- 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。,The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
uart.rar
- 实现串并口通信,共有发送和接受两个模块。,Strings parallel to achieve communication, send and receive a total of two modules.
UART(FPGA)
- 基于现场可编程逻辑器件（FPGA）使用VHDL语言QuartusII实现UART通讯-Based on field programmable logic device (FPGA) using VHDL language QuartusII achieve UART communications
uart
- 基于FPGA的多调制UART的设计，相当不错，可估参考-FPGA-based multi-modem UART design, very good reference to assess
UART
- 包含一个在QUARYUS环境下运行的UART的工程，实际在EP2C20Q240上调试成功的通用串口VHDL程序-The QUARYUS environment contains a UART to run the project, the actual success of the EP2C20Q240 Universal Serial debugging VHDL programs
UART
- 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
uart
- uart接口读写控制器，已经在fpga上测试通过-uart interface to read and write controller, has been tested by fpga
uart
- FPGA中的UART模块，调试通过的哦！！希望对大家有所帮助，呵呵。。。我用的是quartus7.2版本编写的，当然也有些copy网上的-FPGA in the UART modules, debugging through the Oh! ! We want to help, Hehe. . . I use the quartus7.2 version of the written, of course, also some copy online
uart
- UART design with bist capability
uart
- UART串口的VHDL源程序，希望对大家有用-UART serial port of the VHDL source code, we want to be useful
UART
- This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
UART
- 用VHDL实现与电脑串口进行通信。已通过开发板验证正确。开发板时钟50M，波特率19200.-VHDL implementation using serial communication with the computer. Has been verified through the development board are correct.
uart-
- 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
uart-VHDL
- uart-VHDL 带奇偶校验位 比特率为1152-uart-VHDL add parity check bit rate is 115200
UART
- uart通用异步收发器，包括收发模块和。数据产生模块-uart transmit and reciver
UART-VHDL-QUARTUS
- uart vhdl quartus for altera
UART
- 自己总结的UART的设计及分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the design and analysis of UART, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
基于VHDL的UART控制器设计
- UART模块的VHDL语言设计(Design of VHDL language based on UART module)