搜索资源列表
test
- Verilog test file not vhd-Verilog test file not vhd
Rs232sourcecode
- Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to
usb_blaster
- 文件列表(日期：2005080604~2009101613)
8080cpu
- this code for cpu 8080 design -this is code for cpu 8080 design
dingshi
- quarters2编写的定时器.vhd为源程序-prepared quarters2 timer. vhd for source
clk_div.vhd
- 实现对时钟信号的技术分频，程序简单易懂，对于初学VHDL者来说，提供了一个良好的方法。-Implementation of the clock signal frequency technology, the program easy to understand, for the beginner who VHDL, provides a good approach.
dec.vhd
- vhdl code for a 16 bit decoder design
FIFO
- 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
ADC0809VHDL
- 文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Descr ipt
H.264
- H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块-Standard H.264 decoder all verilog source, including intra-, inter-frame, transform coding, entropy coding, filtering all modules
fenpinqi
- 此文件为EDA的8位分频器，但可以用于不同位分频器，如：1位到10位等，用Quartus软件来，以文件VHD格式编译即可-This document is for EDA 8-bit prescaler, the prescaler can be used in different places, such as: 1-10 and so on, using Quartus software to VHD format file can be compiled
Xilinx USB JTAG 下載端程式
- Xilinx USB JTAG 下載端程式 -The jtag_logic.vhd in this directory describes the logic for a parallel-serial converter to be connected to a FT245BM USB chip from FTDI Inc
ad7823.vhd
- ad7823的VHDL驱动程序，测试在quartus9.0下编译通过-ad7823 driver of VHDL, the compiler under test through quartus9.0
FIFO_design_reference_document
- FIFO设计的参考文档 Project name : Fifo -- Project descr iption : Fifo controller Unit 工程名 : FIFO.VHD 用到库文件IEEE.STD_LOGIC_1164-FIFO reference design document Project name : Fifo -- Project descr iption : Fifo controller Unit -
contador
- Contador hexadecimal para UP1 (.vhd)
03.EDK8.2
- 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-
ROM_by_Matlab
- Rom.vhd with Matlab and file hex
baheyouxiji
- 用vhdl写的拔河游戏机代码，后缀名改为vhd即可-the code of baheyouxiji in vhdl
11
- 交通灯的描述，主要是用了VHD的语言来编写的-light
arp3
- it s an audio project