搜索资源列表
F7-2VT-1DR
- 2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH' s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
baudgen_latest.tar
- 波特率发生器的VHDL源码。适用于uart、spi、IIC-Baud rate generator VHDL source code. Apply to uart, spi, IIC
mp3
- MP3解码器的VHDL源代码 ,很实用的，设计时可以参考 ，很罕见的完整MP3 decoder源码 -VHDL code for MP3 decoder
LCD
- lcd verilog hdl 源码 可以直接使用，适用modelsim-lcd verilog HDL source
taxi
- 用verilog写的基于cpld的出租车计费器的源码，需要的参考一下-Use verilog to write a taxi based cpld billing device source code, need to refer to
ram
- 用FPGA做的RAM，源码，调试通过，有工程-FPGA to do with RAM, source code, debugging through, there are works
uart_test_ok_921
- 一个简单的uart 源码，接收一个字符并发回，通过测试，可以使用的，输入时钟12mhz,发送速率96-A simple uart source code, receiving a character and send back through the test, can be used, input clock 12mhz, sending rate 9600
uart_0910
- uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of fr
SDRAM_design_source
- sdram的设计文档和参考源码。嵌入式开发中很难找到的源码。-sdram design documents and source code
Ethernet
- 100base-t4中继器源码！实现8端口100BASE-T4半双工中继器。-100base-t4 Ethernet repeater
fft
- FPGA的FFT变换源码(vhdl语言版)-THE CODE OF fft ,FPGA（VHDL）
FPGA_Book_cd
- 《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，本书内容还是非常丰富的，涉及无线通信领域各个方面。不过对于一些比较新的技术，其FPGA实现部分过于简略，难以在工程中实用化。-" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of
CAN_I2C_USB_yuanma
- CAN总线，I2C，USB等的FPGA实现源码，可以利用原有代码，快速开发出自己的代码，物有所值-CAN bus, I2C, USB, etc. FPGA implementation source code, we can use the original code, and to quickly develop its own code, value for money
UART
- 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
USB
- 用VHDL编写实现的USB接口控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the USB interface controller, bring their own testbench, after decompression project file can be opened with the ISE.
canbus
- 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.
mac_controller
- 用verilog编写实现的以太网控制器（MAC）源码，解压后用ISE打开工程即可。-Prepared using verilog implementation Ethernet Controller (MAC) source code, open the project after decompression can be used ISE.
cpldbus51
- 51单片机与cpld总线连接vhdl源码-51 SCM and cpld bus connection vhdl source code
watchdog
- 看门狗定时器Verilog源码；用于MCU的辅助模块，定时特定的时间来做硬件复位，是用于避免固件跑死的一个机制。-Watchdog verilog source.
Channel_Equalizer
- 802.11a接收机的信道均衡源码，verilog语言的-802.11a receiver channel equalizer source, verilog language