搜索资源列表
cos
- FPGA实现正弦，余弦的计算，verilog语言-FPGA realization of sine, cosine calculation, verilog language
10010
- Verilog状态机设计-10010序列检测器-Verilog state machine design-10010 Sequence Detector
8
- verilog写的 自动售饮料机-written in verilog beverage vending machine
USB_Interface
- verilog USB USB的slave fifo的控制-verilog USB
hdlc_decode
- 基于Verilog的HDLC解码器。其中时钟的提取采用数字锁相环-The HDLC decoder based on Verilog. Which are extracted using digital phase-locked loop clock
CRC16
- 用于CRC16校验的Verilog程序源代码，喜欢的拿走-Uses in CRC16 the verification the Verilog procedure source code, likes taking away
URAT
- Verilog硬件描述语言，RS232串口发送接收程序-Verilog hardware descr iption language, RS232 serial port send and receive program
fir
- 比较简单的16位fir滤波器，16阶，Verilog编写-Simple 16-bit fir filter, 16 bands, Verilog prepared
rom
- 基于verilog的rom存储器 简单实用 初学者的好材料-Rom memory, based on simple and practical verilog' s good material for beginners
MP3_in_CycloneII
- 在FPGA中实现MP3的解码，verilog的，带说明文档。-In the FPGA to implement MP3 decoding, verilog, and with documentation.
ram_Test
- RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
cpu
- verilog编写的简单的CPU，用于参考，已经过仿真-verilog prepared by a simple CPU, for reference, has been simulation
ps2_keyboard
- FPGA PS2键盘驱动设计，使用软件QuartusII6.0 verilog-FPGA PS2 keyboard-driven design, the use of software QuartusII6.0 verilog
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
verilog
- 一个可以综合的Verilog 7段秒表实例。上海交大微电子学院课程作业。-An example Verilog project. 7-segment
NCO
- 用verilog语言写的NCO，在quartus环境中应用-Verilog language written with NCO, quartus environment in the applications
Verilog
- fpga使用代码大全，很有用的，，谢谢下载，我没什么说的了，住学习愉快-fpga using the Code Complete, very useful, Thank you to download, I have nothing to say about it, learning to live happily
lcd-code
- 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
lms
- verilog编写的lms算法模块，简单易用-lms module using verilog.It s simple.
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog