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用Verilog语言实现QPSK调制,QPSK是一种数字调制方式。它分为绝对相移和相对相移两种。
-Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.
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16QAM调制与解调的Verilog语言的功能实现-the realization of 16QAM modulation and demodulation on Verilog language
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八相移键控调制的Verilog程序,给出了各个子模块的程序,实现了信号调制。-Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.
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用Verilog实现FSK调制,调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
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振幅键控ASK的调制解调Verilog实现,带测试文件-ASK amplitude shift keying modulation and demodulation Verilog implementation, with the test file
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基于FPGA的自治型SPWM波形发生器的设计!正弦脉宽调制(SPWM)技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用,如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈!-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit
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1. FSK调制VHDL程序
--文件名:PL_FSK
--功能:基于VHDL硬件描述语言,对基带信号进行FSK调制
-1. FSK modulation VHDL procedures- File Name: PL_FSK- features: VHDL hardware descr iption language based on the base-band signal FSK modulation
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数字通信中的FSK调制解调的原理和过程, 通过用Matlab 对这一过程的编程,分析信号在理想信道和加噪信道中传输时的时域图, 并用蒙特卡罗算法进行仿真。-Digital communications in FSK modulation and demodulation principle and process, through the use of Matlab in the process of programming, analysis of signals in the ideal c
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使用verilog实现全数字16QAM调制器,载波频率1MHZ,数据比特流的速率为100Kbps,-the modulation of 16QAM based on FPGA
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模块化实现2FSK调制,简单易懂非常适合初学者学习参考.-Modular realization 2FSK modulation, easy to understand reference is suitable for beginners to learn.
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来自于ALTERA官方网站。
本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器,不需要采用专门的外部时钟。
附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design
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用于BPSK调制的自行设计,说明如下:
1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵,矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时,受到前后共6个码元的共同影响,所以是由6个码元共同决定。这6个码元是随机的,可能是0也可能是1(双极性时可能是-1也可能是+1),故6个码元共2^6=64种情况,所以产生的矩阵是64*4。最后逐行输出这256个数。
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verilog常用程序及其仿真结果整理,包括LCD,LED,AD采集,URAT,电子琴,电梯控制,自动售货机控制,出租车计价器,电子时钟,频率计,MPSK调制与解调-verilog common finishing process and its simulation results, including LCD, LED, AD collection, URAT, keyboard, elevator control, vending machine control, taxi meter,
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用verilog编写的代码,实现了16QAM调制解调功能-the realization of 16QAM modulation and demodulation on Verilog language
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mak调制的fpga实现程序,基于fpga的vl文件,很好用,实用-mak modulation of fpga implementation procedures based fpga vl file, useful, practical
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正交调制芯片,.v文件,但是没有说明文件,只能作为参考-Quadrature modulation chip,. V file, but no documentation, only as a reference
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基于FPGA的16QAM调制程序,基于verilog开发环境-16QAM modulation program based on FPGA-based development environment verilog
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调制与解调系统的FPGA设计实现,包括2-ASK调制和解调,2-FSK调制和解调,2-PSK调制和解调,QPSK调制和解调,PPM调制和解调的verilog源代码。-FPGA design implementation of modulation and demodulation system, including 2-ASK modulation and demodulation, 2-FSK modulation and demodulation, 2-PSK modulation and
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通过verilog语言实现各种基本信号的调制解调过程,包括2psk,qpsk,ppm(Realize the modulation and demodulation process of various basic signals through verilog language, including 2psk, qpsk, ppm)
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