搜索资源列表
veriloghdl
- verilog语言书籍 夏宇闻的 十分经典 pdf 清晰版-verilog language books pdf Yu Xia Wen a very clear version of the classic
VerilogHDL
- Virlog语言的入门级教程，方便初学者学习并掌握这门语言-Virlog language entry-level tutorials, easy for beginners to learn and master the language
VerilogHDL
- Verilog HDL 硬件语言 生动地描述了Verilog HDL从入门到精通的经典书籍！-Verilog HDL hardware descr iption language Verilog HDL vividly from entry to the master' s classic books!
ad7862
- 运用VerilogHDL实现AD7862的数据采集设计-using VerilogHDL by AD7862 to collect data
VerilogHDL
- 这是学习Verilog的好的课件！！分享给大家，希望可以互相帮助。-It is good to learn Verilog courseware! ! We share the hope that you can help each other.
verilog_hdl_135
- veriloghdl教程135例是对初学者的引导，挺好的，要慢慢看-verilog hdl is a beginners tutorial 135 cases of guidance, in very good shape, it is necessary to wait and see
VerilogHDL
- Vhdl langerang is akiund tool of EDA-Vhdl langerang is akiund tool of EDA
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
VerilogHDL
- 很不错的一本书，学习verilog hdl 必备-A very good book to learn verilog hdl essential ~ ~
verilogHDL
- 用Verilog HDL语言实现通用异步收发URAT装置-With the Verilog HDL language to achieve universal asynchronous receiver URAT Device
paobiao
- 基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube sho
RS232_Interface
- verilogHDL串口逻辑,波特率为96-verilogHDL serial interface logic
PKUverilogPPt
- 北京大学VerilogHDL学习课件，很不错-Peking University VerilogHDL Learning Courseware
verilog_hdl_135_examples
- 135个经典VerilogHDL源码和说明文档，入门的好资料-135 Classic VerilogHDL source and documentation, a good data entry
verilogHDL
- Verilog学习资料，内容详尽，是初学者的最好资料-Verilog learning materials, content, detailed information is the best for beginners
digi_clock
- VerilogHDL程序，功能是可以实现一个数字电子时钟。-It s a Verilog-HDL procedure which can makes a digital electronic clock.
ddr_contrl
- DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL.
VerilogHDlclock
- 基于VerilogHDL设计的多功能数字钟-Based on the design of the multi-function digital clock VerilogHDL...
3508c54266f8407719e18880fd6addd6
- 是用VerilogHDL语言写的有关SDRAM的源代码。-VerilogHDL language is written in the SDRAM of the source code.