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VerilogHDL
- 适合于硬件描述语言的入门学习资料 强烈推荐适合于已经有一定的语言基础-Hardware descr iption language suitable for entry-learning materials has been strongly recommended for a certain language-based
GrayCnt
- 格雷码计数器 VerilogHDL语言编写-Gray-code counter using VerilogHDL language
8051core-Verilog
- 利用VerilogHDL语言，编程实现8051单片机的功能，在FPGA的工程中有广泛的应用-Use VerilogHDL language programming 8051 microcontroller functions in FPGA projects in a wide range of applications
manch
- 该文件是一个完整的工程文件，用VerilogHDL语言编写，包括曼彻斯特编码器的设计文件和仿真测试文件以及解码器的设计文件和仿真测试文件。在Modelsim中仿真测试通过。-The document is a complete project file, with VerilogHDL languages, including the Manchester encoder design documents and simulation test files and decoder design
xilinxfpga
- Xilinx FPGA VerilogHDL 典型入门实例-Xilinx FPGA VerilogHDL
MANCHESTER_DECODER
- 射频识别防碰撞算法，用veriloghdl编写。-RFID anti-collision algorithm
simple_counter
- 改程序完成了计数功能，用到Veriloghdl编程实现，竟FPGA下载验证通过-To change the counting process is completed, use Veriloghdl programming, actually verified by FPGA Download
Verilog
- 该代码是Veriloghdl语言实现的串口通信，经过FPGA板子下载验证通过，读者可以使用-The code is Veriloghdl language of the serial communications, after verification by FPGA board download, readers can use
verilog232
- 该源码是关于Veriloghdl语言编写的rs232串口实现，通过下载得到验证-The source code is written in on the Veriloghdl rs232 serial interface, be verified by downloading
veriloghdl
- Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的 数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。-Verilog HDL is a hardware descr iption language, used from the algorithm level, gate-level to switch level design of a variety of
VerilogHDL(1-7)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
VerilogHDL(8-10)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
VerilogHDL(11-13)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
VerilogHDL1
- FFT的VerilogHDL实现 很有实用价值，值得下载-FFT' s VerilogHDL achieve great practical value, worth downloading
VerilogHDL
- Verilog HDL设计要点在前面学习的基上， 通过本章十个阶段的练习，能逐步掌握Verilog HDL 设计的要点。可以先理解样板模块中每一条语句的作用，然后对样板模块进行综合前和综合后仿真，再独立完成每一阶段规定的练习。-Verilog HDL design points in the previous study based on ten stages of practice by this chapter, can gradually grasp the main points of
veriloghdl
- verilog hdl硬件描述语言，其中讲述了十个例子，帮助大家学习verilog hdl硬件描述语言。-verilog hdl hardware descr iption language, which describes 10 examples to help you learn verilog hdl hardware descr iption language.
mul8b
- 有VerilogHDL编写的8位乘法器，可以综合。-Have been prepared in 8-bit multiplier VerilogHDL can be integrated.
crc5
- 用VerilogHDL编写的CRC5校验，可以综合。-Check with VerilogHDL CRC5 prepared, can be summarized.
lfsr
- 用VerilogHDL编写的lfsr移位寄存器，可以综合。-Lfsr prepared with VerilogHDL shift register, can be summarized.
send
- 用VerilogHDL编写的串口发送模块，可以综合。-VerilogHDL prepared using serial transmission module, can be integrated.