搜索资源列表
Verilog_Modulation
- VerilogHDL那些事儿_建模篇（for DB4CE15）-VerilogHDL those things _ Modeling articles (for DB4CE15)
RX_SYN
- OFDM接收机新型同步算法的实现，采用verilogHDL语言，经测试性能良好-OFDM receiver to achieve the new synchronization algorithm, using verilogHDL language, good performance tested
RX_RS_DEC
- OFDM系统新型RS编解码的verilogHDL设计，经测试误码率性能提高-OFDM system verilogHDL new RS codec design, improved bit error rate performance tested
RS_CC_ENC
- OFDM系统新型CC编解码的verilogHDL设计，与RS编码级联，经测试误码率性能提高-OFDM system verilogHDL new CC codec design, coding and RS cascade, tested BER performance improvement
verilogHDL
- 自己写的一些Verilog HDL小程序，来自课本的例程-Verilog HDL himself wrote some small programs, routines from textbooks
VerilogHDL_-03
- VerilogHDL a guide to digital design and synthesis
Project-8
- 课程设计时用verilogHDL写的MIPS CPU-MIPS CPU coded with Verilog HDL
adder_sub_mul
- 加法器，减法器，乘法器，超前进位，一位拓展成四位-adder and subber are written by the language of VerilogHDL one bit to four bits.
regfor24
- 这是一个24小时时钟，整体使用verilogHDL编写，六位数码管显示，分为三个模块，分别为扫频模块，计时显示模块，和顶层模块-it s a clock for 24 hours .use verilogHDL to write the project ,it s easy to understand.
VerilogHDL_PIC16c_Microcontroller
- VerilogHDLPIC16c - VerilogHDL implementation of PIC16c5x
baud_gen
- 用veriloghdl语言编写的时钟分频程序-Veriloghdl language with clock division program
uart_rx
- 用Veriloghdl语言编写的串口接收程序-Veriloghdl language with serial receiving program
uart_tx
- 用Veriloghdl语言编写的串口发送程序-Veriloghdl language with serial transmission program
24bitdivderVerilog
- FPGA 24位除法器编程,verilogHDL编程-The 24 bit divder used in FPGA，programmed in verilog HDL.
original-1-by-16-bit-multiplier
- 原码一位乘16位乘法器 用VerilogHDL语言实现-Original code A by 16-bit multiplier VerilogHDL language used to achieve
lcd12864
- lcd12864液晶显示 Verilog语言-lcd12864 VerilogHDL
key_led
- led灯按键控制 VerilogHDL 始于FPGA入门学习-led control VerilogHDL
QPSK
- 这是关于QPSK调制解调的VerilogHDL语言的代码，还有用Modelsim仿真的工程文件。testbench都已经写好了。-This is the QPSK modulation and demodulation of VerilogHDL language code, as well as with Modelsim simulation project file. testbench have been written.
m_xulie
- 这是用verilogHDL写的m序列发生器，简单易用，代码非常易读-It is written verilogHDL m sequence generator, easy to use, the code is very easy to read
AD_TLC549
- 这是用verilogHDL写的AD549的FPGA驱动代码，适用于通常的串行AD芯片-It is written in AD549 verilogHDL the FPGA driver code, applicable to the general serial AD chip