搜索资源列表
eeprom_test
- eeprom的读写程序 veriloghdl实现 基于xilinxsparten6-eeprom literacy program veriloghdl Based xilinxsparten6
31_Greedy_snake
- 贪吃蛇小游戏 verilogHDL语言描述 基于xilinxsparten6板子 -Snake game verilogHDL descr iption language based xilinxsparten6 board
key
- 用硬件描述语言VerilogHDL完成Basys2键盘扫描设计模块。-Using hardware descr iption language Basys2 to complete the VerilogHDL keyboard scan design module.
tanchishe
- 用硬件描述语言VerilogHDL完成基于FPGA、VGA的简易贪吃蛇设计。-Using hardware descr iption language VerilogHDL to complete the simple Snake design based on FPGA and VGA.
fanggeyidong
- 用硬件描述语言VerilogHDL完成基于FPGA、VGA的方格移动设计。-Using hardware descr iption language VerilogHDL to complete the FPGA, VGA based on the design of the grid.
conv313
- 卷积码编译码（3，1，3）的编码verilogHDL程序-Convolution code codec (3,1,3) coding verilog HDL program
lcd1602_testshiyan4
- 液晶lcd1602的verilogHDL显示程序-verilog HDL lcd1602 liquid crystal display program
baseonFPGAclock
- 用verilogHDL语言写的基于FPGA的电子钟。里面包含闹钟、秒表、日历、时间设置等功能，可用LCD显示-verilog language, implemented on the FPGA alarm clock, calendar, time display, stopwatch in one of the electronic clock and calendar. Can be displayed on LCD
example20-LCD12864
- FPGA 12864lcd驱动程序，verilogHDL语言开发，可直接使用。-FPGA 12864 lcd driver, verilog HDL language development, it can be used directly.
IDCT
- HEVC是正在研发的新一代视频编码标准。 本文面向HDTV应用，设计兼容HEVC标准的两位整数IDCT电路， 通过对IDCT的特点进行分析，完成了电路的架构设计, 采用较为节省面积的做法和流水线结构，并进行VerilogHDL代码设计-High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architect
ADconversion
- Veriloghdl 代码使用ADC0809来进行ad转换，使用verilog hdl程序来进行ad转化-Veriloghdl ad code uses ADC0809 to convert, using the verilog hdl program to ad conversion
pic
- 贪吃蛇小游戏 VerilogHDL，FPGA，QUARTUS-Snake game VerilogHDL, FPGA, QUARTUSII
09_SDRAM_VGA_Display_Test640480
- 在quartusII的开发环境下，编写的VerilogHDL语言的SDRAM通信程序，欢迎下载，这是基于Crazybingo的板卡环境设计-Under the development environment of quartusII, write SDRAM VerilogHDL language communication program, welcome to download, this is based on Crazybingo board environment design
VerilogHDL
- 这是verilog硬件描述语言的一些知识，比较全面。值得下载。-This is verilog hardware descr iption language, some knowledge, more comprehensive. Worth downloading.
UART
- verilogHDL语言实现的uart模块，内部包含波特率生成、uart收、uart发三个子模块，支持配置常规波特率、数据位、结束位和校验位，输入工作时钟125M，时钟不一样时需要修改波特率生成的代码-verilogHDL language of uart module contains an internal baud rate generator, uart receive, uart made three sub-module, configured to support conventi
9_eeprom_test
- 基于Cyclone IV系列FPGA的eeprom驱动程序，Verilog语言编写。-eeprom driver based Cyclone IVhardware，use VerilogHDL.
13_flash_test
- 基于CycloneIV的SPI Flash驱动程序，采用VerilogHDL硬件语言编写，经测试正常.-SPI Flash driver program,use Verilog HDL,successfully tested.
15_usb_test
- 用VerilogHDL编写的USB驱动程序，经过了成功的测试.-USB driver program with VerilogHDL,successful tested.
Use-lab2-ISE-software
- 熟悉掌握VerilogHDL语言并能用其建立基本 的逻辑部件在Xilinx ISE平台进行输入、编辑、 调试、仿真-Familiar with Verilog HDL language and be able to establish its basic logical components in Xilinx ISE platform for input, editing, debugging, simulation
ads7822
- 串行AD的VerilogHDL程序,验证过，成功了-SERIAL AD VerilogHDL