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MSC8156ADS-Reference-Manual
- freescale 飞思卡尔 8156 6核 TD-LTE 基带基站开发手册，专用于4G TD-LTE enodeb 基站基带板开发，该芯片被广泛应用于中兴/ALU/摩托罗拉 4G基站。-the freescale Freescale 8156 6core TD-LTE baseband base station development manual, dedicated to the 4G TD-LTE enodeb base station baseband board developmen
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
Modifying single datapath
- We had to modify the single cycle datapath to support the execution of the following instructions: addi, ori, andi, xori, xor and bne; in addition to the instructions supported. Our datapath had to include all necessary functional units with connecti
4-bit-ALU
- it is a 4 bit airthmatic logic unit in which all basic mathematical operation of binary number can done. it is a vhdl code file
ALU
- 8-bit unsigned, 16 operations(arithmetic and logic).
barrel_shifter
- A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an implementation the output of one mux is connected to the inp
cpu
- 这是本人的课程设计。采用微程序控制的CPU，能够从RAM中读取指令，并执行。包含MBR,MAR,IR,BR,ALU,PC等功能部件，能实现加减乘法，逻辑左右移位，逻辑与或非，在此基础上还可以拓展。希望能帮助你们。-This is my curriculum design. Micro-program control CPU can read instructions from the RAM and executed. Contains the MBR, MAR, IR, BR, ALU, PC
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
cpu
- 本代码主要通过VHDL语言描述了一个CPU，包含了MAR,MBR,PC,BR,ALU,ACC等一系列寄存器。-The code is mainly described by VHDL language a CPU contains a series of MAR, MBR, PC, BR, ALU, ACC register.
8051-IP
- The synchronous 8051 microcontroller is a common processor found in many embedded systems. By using asynchronous design techniques, the performance of the 8051 microcontroller is increased. Through simulation and the use of existing synchronous
mipsfiles
- 多周期的cpu 中alu模块设计 打算打打msn代码三年大开杀戒-cpu alu
fpga1
- This the VHDl file of ALU compiler that can generate +-/* of 4 bit no.-This is the VHDl file of ALU compiler that can generate +-/* of 4 bit no.
VHDL_book2
- add4a：4位加法器的设计 add8a：8位加法器的设计 subtract：4位减法器的设计 addsub： 4位加法器/减法器的设计 shift4：移位寄存器的设计 mult4：乘法器设计 div8：除法器设计 alu4：算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit ad
ALU_exercise
- 弗莱堡大学VLSI课程ALU练习，希望对大家有帮助-University of Freiburg VLSI courses ALU practice, we hope to help
BCD_ALU
- bcd码的ALU单元，包含全加、全减、乘法、除法器-bcd code ALU unit, including All-Canadian, all subtraction, multiplication, division, unit
cpu8bit
- 这是一个计算机组成原理综合性实验：设计8位cpu。该cpu是8bit的代码，包含有4个寄存器，一个存储器，还有alu以及控制器。一共可以实现16条指令。-This is a computer composition principle of comprehensive experiment: Design 8 cpu. The cpu is 8bit code contains four registers, a memory, as well as alu and controllers. A
CAL
- 基于BCD码的十进制ALU设计，可实现加减乘除的功能-BCD to decimal ALU based design can achieve the arithmetic function
alu_testbench_vhdl_689102300
- ALU的testbench测试，可联合仿真使用-The ALU testbench test can be co-simulation using
16-bit-alu
- arithmetic and logic unit of sixteen bit