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Sonic_2
- FPGA开发超声波测距,可改写工业探伤或倒车测距等系统,quartus2下选择EP2C5Q208C8(CycloneⅡ) 支持目前淘宝上能买到的所有4-5针超声波模块 应用cycloneⅡ自带除法模块 开发板为有光技术YG2.1 生成电路规模较小 !!注意:移植程序仅需重新约束数码管和超声波模块的针脚-Ultrasonic Ranging FPGA development, industrial inspection or reverse rewritable ranging
hdlrecord
- Bluespec sample program and program for comparator. Cyclone 2 FPGA Real Time Clock program.
rapport_vhdl
- Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone -Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone II
c
- 主要用于旋流器中的壁面系数的设置,编写程序,面设置壁需要不必要的-Mainly used to set the cyclone in the wall coefficient, programming, set the wall surfaces require unnecessary
vga_test
- 基于nios的vga控制器,分辨率及显示区域,显示位数,显存深度可调整,已经在altera cyclone ii条件下测试通过 quartus13.0开发环境 主机端符合avalon标准-VGA controller based on NIOS, resolution and display area show the median, the memory depth can be adjusted, has been in Altera cyclone II under the conditi
pll_prj
- PLL配置仿真实验 PLL,即锁相环。简单的理解,给PLL 一个时钟输入(一般是外部晶振时钟), 然后经过PLL 内部的处理以后,在PLL 的输出端口就可以得到一定范围的时钟频 率。其之所以应用广泛,因为从PLL 输出得到的时钟不仅仅从频率和相位上比较 稳定,而且其时钟网络延时也相比内部逻辑产生的分频时钟要小得多。-Altera FPGA Cyclone
ECE-127
- This codes are pattern identifier implemented on Field Programmable Gate Array (FPGA). The board used is cyclone IV De2-115.
demo8-ps2_1_vhdl
- ep1c3实现ps2 Assembler Status Successful - Fri Aug 27 17:48:36 2010 Revision Name ps2_1 Top-level Entity Name ps2_1 Family Cyclone Device EP1C3T144C8-ep1c3 realize ps2,ep1c3 realize ps2,ep1c3 realize ps2
CBM
- 已经对SQL注入,JS恶意攻击及 5C暴库做了预防 管理员账号:cyclone 管理员密码:cyclone-Already SQL injection, JS 5C malicious attacks and violence prevention libraries do Administrator account: cyclone Administrator Password: cyclone
vga_with_hw_test_image_v1_0
- vga image controlleur cyclone 2
DB4CE15
- Altera公司出品的FPGA IV cyclone DB4CE15核心板的电路原理图 -Altera' s FPGA IV cyclone DB4CE15 produced core plate circuit schematics
8phpfile_2.6.7
- 设置里支持更换更换服务器 更换了更新服务器(经过多次测试 自动更细完全稳定推荐大家用 页脚的检查更新升级) 支持 远程下载文件 支持进度条 支持 解析 迅雷 网际快车 旋风 地址下载 更新了 发送邮件选择附件 的界面 现在能看到选择了那些附件-Supports the replacement server settings where replacement Replacing the update server (after several tests automati
myfft
- 锁相环程序,适用于cyclone III,产生100kHz时钟信号。-Phase-locked loop program, suitable for cyclone III, produce 100 KHZ the clock signal.
BCD_ADDER_TOP
- cyclone三系列,EP3C10E144CB的 8421BCD码加法器 -quartus 8421BCD-ADD-led
D7xiazaidizhizhuanhuanjiemi
- 用delphi7写的下载地址的解密和转换,支持快车,旋风及迅雷的地址相互转换和解密成普通可下载地址-Written in delphi7 download address decryption and transformation, support express, cyclone and the thunderbolt address transformation and decryption into ordinary can download address
AD_24bit_Group_25_CYC4
- 高精度24位ADC时钟配置和数据读取程序,基于Altera cyclone IV EP4CE22F17C6N-High-precision 24-bit ADC clock configuration and data reading program, based on Altera cyclone IV EP4CE22F17C6N
9_eeprom_test
- 基于Cyclone IV系列FPGA的eeprom驱动程序,Verilog语言编写。-eeprom driver based Cyclone IVhardware,use VerilogHDL.
pwm
- VHDL, quartet 2 , FPGA, cyclone II, controllen PWM brightness
DE2-115 Ephoto
- The 4.3" Ultra-high Resolution LCD Touch Panel Development Kit provides users a 800x480 full-color high-quality LCD Touch Panel with complete reference designs and source code allowing users to develop applications by a touch panel on the Altera
05_NIOS_SRAM
- 利用FPGA的NIOS 2控制SRAM。FPGA的型号为Altera 的Cyclone 4。-Of FPGA NIOS 2 control SRAM. Altera' s FPGA model for the Cyclone 4.