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delayandGMSKdemod
- GSM中，GMSK解调与延迟程序，Verilog HDL。-GMSK DEMOD
vga_fpga
- 详解介绍vga的verilog hdl编程原理，和vga原理和方法，程序详解等。-Xiang Jie introduced the verilog hdl programming principles vga, and vga principles and methods, procedures, etc. Xiangjie.
adder
- 一个加法器程序,同时里面又有一个测试程序，是学习verilog HDL的好程序。-a adder program
clock
- 这个程序是用verilog hdl语言编写，实现在数码管上显示时间，暂不支持调整-This program is written in verilog hdl to achieve in the digital tube display time, withhold support to the adjustment
Frequency_Measurement
- 测频程序 C51 Verilog HDL-Frequency Measurement C51 Verilog HDL
chengxu
- 加法器 比较器verilog hdl 等简单小程序 新手学习中 见谅-Adder comparator verilog hdl Adder comparator verilog hdl a small way as simple novice learning apologize
uart
- 基于verilog HDL编写的串口通讯接口uart程序-Prepared based on verilog HDL uart serial communication interface program
SwitchLed
- FPGA入门程序。适合编程初学者的学习。由开关控制LED灯的亮灭。ISE集成开发环境。Verilog HDL语言编写-FPGA entry procedures. Programming for beginners to learn. LED lights from the light switch control off. ISE Integrated Development Environment. Language Verilog HDL
Verilog_shuzisheji
- 本章的目的是想通过对数字信号处理、计算（Computing）、算法和数据结构、编程语言和 程序、体系结构和硬线逻辑等基本概念的介绍，了解算法与硬线逻辑之间的关系从而引入 利用Verilog HDL 硬件描述语言设计复杂的数字逻辑系统的概念和方法。向读者展示一种 九十年代才真正开始在美国等先进的工业国家逐步推广的数字逻辑系统的设计方法-Purpose of this chapter is to through digital signal processing, computing (
DesignCompilerPPT
- 用design compiler对verilog hdl的程序进行逻辑综合最后生成门级网表即用门生成的电路图。-Verilog hdl with design compiler of the logic synthesis procedure generates the final gate-level netlist that is generated with the door circuit.
mux6
- 多路开关程序，verilog HDL编写，在FPGA里面实现，已经通过。-writing by verilog HDL program for FPGA application,complied successfully.
baweishumaguan
- 利用Verilog hdl语言编写的8位数码管程序，这对于那些刚学Verilog hdl语言的学习者来说，是不错的入门程序，特别程序里头的分频程序模块，谢谢支持。-Using Verilog hdl language of the eight digital control procedures, which for those just learning Verilog hdl language learners, is a good entry procedures, especially
VHDL_Examples_foreducation
- 一些Verylog HDL的小程序，自己琢磨一下啊-VERYLOG HDL
Verilogintrc1
- Verylog HDL 一些小程序，可以借鉴一下-Verylog HDL
dac8552
- 使用Verilog HDL语言编写的实现DAC8552的时序程序，单片机总线与CPLD/FPGA通信，单片机负责控制送数实现功能。-Use Verilog HDL language DAC8552 realization of temporal procedures, SCM bus and CPLD/FPGA communication, SCM control to send several functions.
fir_srg
- 该程序是利用Verlag HDL硬件描述语言实现的fir数字滤波器，希望对刚学习verilog的朋友有所帮助。-The procedure is to use Verlag HDL hardware descr iption language implementation of fir digital filters, just want to help a friend learn verilog.
music
- 用FPGA实现的歌曲“梁祝”播放程序，用Verilog HDL编写-FPGA implementation with the song " Butterfly Lovers" player, written with Verilog HDL
altpcie_64b_x8_pipen1b
- PCIE的软核程序，基于Verilog HDL语言，应用于FPGA的高级编程应用中。-PCIE soft nuclear program, based on Verilog HDL language, used in high-level FPGA programming applications.
BCD
- BCD码减法实现程序，非常完整，采用Verilog HDL语言实现。-BCD subtraction to achieve program code, very complete, using Verilog HDL language.
EDA
- 程序是用verilog HDL语言写成的抢答器，已经进过测试，绝对可以运行-Program is written in verilog HDL Responder, has been to test, absolutely you can run