搜索资源列表
Verilog-HDL--MODEL
- Verilog HDL程序设计教程verolog代码设计，包含各种基本代码-Verilog HDL programming tutorial verolog code design, includes a variety of basic code
DDR3-SDRAM-Verilog-Model(1)
- contains the information and codes of DDR3 memory model
8051core-Verilog
- 用verilog语言描述的8051模型,里面包括逻辑运算单元，进位单元，存储器单元-describe the model of 8051 with verilog
QuartusII_SPI
- 這個是SPI Model Verilog Code 已經透過Quartus II 完成 Compiler 沒有問題 -This is the SPI Model Verilog Code has been completed through the Quartus II Compiler no problem
DDR3-SDRAM-Verilog-Model
- ddr3模型以及代码和测试程序，不过带有小瑕疵-ddr3 model and code and test procedures, but with small flaws
usb_sim_model
- EZ-USB的仿真模型，Verilog实现，能够实现端点传输，自用。-EZ-USB simulation model, Verilog implementation, to achieve the endpoint transmission, personal use.
M25P128_model
- M25P128（NOR FLASH）的仿真模型，Verilog实现，调试了很久才通，现在基本功能完整，仿真时打印调试信息，自用无问题。-M25P128 (NOR FLASH) simulation model, Verilog implementation, commissioning a long time to pass, and now the basic functions of a complete, print debug information during simulation,
norflash-model
- norflash verilog hdl simulation model
DDR3-SDRAM-Verilog-Model
- 官方网站的verilog语言描写的ddr3 sdram仿真模型。各种型号可选。
Verilog-DATAS-xiayuwen
- 3.1 引言 3.2 Verilog HDL基本结构 3.3 数据类型及常量、变量 3.4 运算符及表达式 3.5 语句 3.6 赋值语句和块语句 3.7 条件语句3.8 循环语句 3.9 结构说明语句 3.10 编译预处理语句 3.11 语句的顺序执行与并行执行 3.12 不同抽象级别的Verilog HDL模型 3.13 设计技巧-3.1 Introduction 3.2 Verilog HDL basic structure 3.3
DLL-verilog
- verilog model of a D-verilog model of a DLL
vscnfet_1_0_1
- CNFET VS-MODEL verilog-A 描述，用于Hspice仿真模型，优化MOSFET性能- stanford
en.SPI_EEPROM_Verilog_models_V10
- spi接口的eeprom模型，型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)
93xx66x Verilog Model
- verilog model for 93xx6xx
i2c_24c64
- 基于verilog的i2c接口EEPROM 24lc64的测试程序，包括了eeprom的虚拟模型，实际在硬件上验证没问题，也可以通过modleism进行仿真(Verilog based I2C interface EEPROM 24lc64 testing procedures, including the virtual model of EEPROM, the actual hardware verification is no problem, you can also simulate
pudn
- Encoders, decoders and RAM Model
eetop.cn_uart 源码 (Verilog)
- Verilog编写的UART通信模块，比较清晰(UART model wrote by Verilog)
test_uart
- 该资料包含用FPGA（EP4CE22F17型号）编写的UART通信程序，最重要的是里面含有串口波特率可调，包括一些常见的波特率。(This information includes UART communication program written by FPGA (EP4CE22F17 model), and most importantly, it contains serial port baud rate tunable, including some common baud rate
y1
- FPGA input clock frequency 50Mhz, try to design a frequency divider to realize 1Hz count signal. Requirements: writing design modules; Write the test model.
eeprom
- 亲自编写并测试通过的 E2PROM 的Verilog代码，由于仅是研究学习之用，功能可以自己添加，继续完善。(The Verilog code of E2PROM is written and tested by itself. As a result of research and learning, functions can be added and perfected.)