搜索资源列表
mult4x4
- 4*4乘法器的源代码，利用FPGA的查找表实现，是数字电路和FPGA的经典乘法器源代码-4* 4 multiplier source code, FPGA lookup table to achieve classic digital circuit and FPGA multiplier source code
new_yasodai_code
- ile Format: PDF/Adobe Acrobat - Quick View by SS Basha - 1963 - Related articles HIGH SPEED MULTIPLIER FOR ALU S USING MINIMAL ... VHDL codes for 8x8-bit signed numbers and successfully simulated and .... a partial product is generated from the m
Jammuna_code
- ile Format: PDF/Adobe Acrobat - Quick View by SS Basha - 1963 - Related articles HIGH SPEED MULTIPLIER FOR ALU S USING MINIMAL ... VHDL codes for 8x8-bit signed numbers and successfully simulated and .... a partial product is generated from the m
old_yasoda_code
- Jul 11, 2012 – Design of Efficient Multiplier Using Vhdl - download or read online. ... presents an efficient implementation of high speed multiplier using the array multiplier,shift & add algorithm,Booth ..... VHDL code for booth multiplier radix 4
akila
- Jul 11, 2012 – Design of Efficient Multiplier Using Vhdl - download or read online. ... presents an efficient implementation of high speed multiplier using the array multiplier,shift & add algorithm,Booth ..... VHDL code for booth multiplier radix 4
alarm_clock
- File Format: PDF/Adobe Acrobat - Quick View by K Bickerff - 2007 - Related articles With delay proportional to the logarithm of the multiplier word length, column compression .... 2.1 A square version of a 4 by 4 array multiplier (after [23]) . .
signed_mult17b_addtree-
- 实现了17乘以17的带符号位的乘法器，采用流水结构，加法树结构-relize a multiplier by using add-tree and level archtiture.
boothradix4
- VHDL code for Radix 4 booth multiplier
mult32
- 4-cycle 32bit-Multiplier that can be work in FPGA. Correct work is confirmed by SP605 FPGA from Xilinx.
200711-0054-05
- TMS28335初始化完成之后， 1、 先DDS产生73.35hz的方波。（问流量管固定频率） 2、 乘法器的另一个数字端输入乘数直接给一个固定值（按照5v），系数是固定的就是对应PID输出的那个接口，串行十二位信号输出（需要先定好一个GPIO接口）。 3、 再延迟一定的时间0.1s或其他时间之后，开始ad采集信号，分别采两路AD信号，此时不稳定（为什么要等到一定的幅值才开始采集AD信号） 4、 选择250点估计一个频率，频率估计的方法采用计算峰值次数的方法或者过零点，总之是为了
fft
- 五阶FFT滤波器设计，verolog实现，只采用乘法器，分时实现。-Fifth-order FFT filter design, verolog, using only the multiplier timeshare achieve.
ssb
- ssb的调制与解调，包括信号的产生、乘法器、加噪、BPF、解调等部分。-ssb modulation and demodulation, signal generation, multiplier, adding noise, BPF, demodulation section.
Calculator
- 这是我自己编写的计数器，可以实现加减乘数的计算-This is what I have written counter subtraction multiplier calculated
VHDL_Bough_64-bit-twos-complement-multiplier
- VHDL Ccode_Booth two s complement multiplication
DDS-ADI
- DDS开发基本原理 基于查询相位的倍频器-DDS to develop basic principle is based on the query phase frequency multiplier
ade
- 用verilog HDL语言实现一个8位串行乘法器-An 8-bit serial multiplier with Verilog HDL language
mul_addtree
- 用verilog HDL语言实现一个4位的流水线乘法器-Achieve a 4-bit pipelined multiplier using Verilog HDL language
5-6
- 用verilog实现节省乘法器的16位复数乘法-16-bit complex multiplication verilog to achieve savings multiplier
booth
- 运用Booth算法的乘法器实现，资源最优，精度较高。-how to implememt multiplier based on Booth algorithm.
test
- dac900驱动，使其产生正弦波，其中关于ram的查询以及pll倍频模块，该代码只是总的调用-DAC900 driver to produce a sine wave, which RAM query and PLL multiplier module, the code is just the total number of calls