搜索资源列表
verilog-pll
- 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
Verilog_EX
- 移位乘法器/流水线乘法器,流水线结构的基本应用-Pipelined multiplier
multi_CX
- 实现8*8串行乘法器的verilog源代码,经过调试的哦!-8* 8 serial multiplier verilog source code, after debugging Oh!
multi_4bits_pipelining
- 实现4*4流水线乘法器的verilog源代码,在FPGA板上运行-4* 4 pipelined multiplier verilog source code, running on the FPGA board
multiplier_ip
- 基于IP核的乘法器设计,完整的设计工程文件在multiplier_ip文件夹下-IP-based core multiplier design, complete design engineering file multiplier_ip file folder
multiply_shift_add
- 基于移位相加运算的乘法器设计,完整的设计工程文件在multiply_shift_add文件夹下-Multiplier design based on shift and add operations, complete design engineering file multiply_shift_add file folder
verilog
- 最长的那个句子,求sum的赋值语句就是FIR滤波器的计算过程,将二进制乘法转化为移位运算。对于小数点后的乘数是向左移,小数点前的乘数是往右移位。 -The longest sentence, find the sum of the assignment statement is the calculation of the FIR filter, the binary multiplication into shift operation. Multiplier after the deci
Multiplier4b
- This a code of a multiplier for two 4 bits numbers written in Verilog.-This is a code of a multiplier for two 4 bits numbers written in Verilog.
FUAD
- Multi SSH. This software can open multiplier ssh. This software using bitvise tunnelier.
SpRegKL1
- 基于交替方向乘子法的核稀疏表示算法,其中约束为L1规则-Alternating direction multiplier method based on nuclear sparse representation algorithm, which is L1 constraint rules
ADMNMF
- 基于交替方向乘子法的非负矩阵分解算法,主要用于盲分离-Alternating direction multiplier method based on non-negative matrix factorization algorithm, mainly used for blind source separation
PHR_multiplier_method
- 《最优化理论与方法》书籍中的乘子法的源程序,该书中的很多案例都用此方法试验过,本代码是一个小案例,将目标函数和约束函数按自己的需求换掉就能进行所期望的运算-" Optimization Theory and Methods" books multiplier method of the source, the book' s many cases are tested using this method, the code is a small case, the obj
07
- 物资管理是企业管理非常重要的一环,它对企业的发展起着非常举足轻重的作用。由于物资的种类繁多,在各部门进出频繁,使得物资管理变得十分复杂。开发一套完善的物资管理系统不但可以使物资的管理者,能够对物资的整个流程状态、库存状况了如指掌,并为决策管理提供科学依据,从而提高了管理水平和工作效率,而且可以使工作人员甩掉手工记账方式,从而最大限度地减少了手工操作带来的失误,达到事半功倍的效果。物资管理系统作为企业管理自动化、规范化的一部分,对提高企业管理效率、提高企业经济效益发挥不可替代的作用。-Materi
16-bit-parallel-mult
- 16位并行乘法器, 由四个4位乘法器组成-16-bit parallel multiplier, consisting of four four multipliers
booth
- 比较好的带符号数乘法的方法是布斯(Booth)算法。它采用相加和相减的操作计算补码数据的乘积。Booth算法对乘数从低位开始判断,根据两个数据位的情况决定进行加法、减法还是仅仅移位操作。-Signed multiplication better approach is to Booth (Booth) algorithms. It uses the operation of addition and subtraction calculations complement data of the
VHDL_book2
- add4a:4位加法器的设计 add8a:8位加法器的设计 subtract:4位减法器的设计 addsub: 4位加法器/减法器的设计 shift4:移位寄存器的设计 mult4:乘法器设计 div8:除法器设计 alu4:算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit ad
PLL_test
- 基于DSP6713,对DSP内的锁相环相关的寄存器进行设置,实现锁相环倍频功能,DSP入门级资料。-Based on the DSP6713, the DSP phase-locked loops in the relevant register set, realization of PLL frequency multiplier function, DSP entry-level data.
Calculator_V1.1
- VS2010环境下编写的简单计算器,能够实现加减乘数功能,适用于初学者。-VS2010 environment to prepare a simple calculator, subtraction multiplier function can be achieved, for beginners.
carry_save_mult
- 常用乘法器设计 样例程序-Common Multiplier sample program
ff_mul
- 伽罗华域GF(q)乘法器设计-Galois field GF (q) Multiplier