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festimate1q1023
- 平方倍频法，估计直接序列扩频qpsk信号载频,功率谱估计法采用平均周期图法-Square multiplier method, the estimated direct sequence spread spectrum qpsk signal carrier frequency, power spectrum estimation method using the average periodogram
A
- 四位二进制乘法器的设计，通过设计我们可以掌握计算机的乘法运算方法，了解Maxpuls软件-Four binary multiplier design, we can master the computer through the design multiplication methods to understand Maxpuls Software
16bits_multiplier
- 这是一个有符号的16位乘法器的设计，包含详细的设计报告和全部的verilog代码。乘法器采用booth编码，4-2压缩，超前进位结构-This is a signed 16-bit multiplier design, detailed design reports and contains all of the verilog code. Multiplier using booth encoding ,4-2 compression, lookahead structure
multi8X8
- 基于vhdl的8为乘法器，移位相加原理，使用VHDL语言-Based on the multiplier vhdl 8, displacement add principle, the use of VHDL language
EX4
- 基于FPGA的16位乘法器，入门的可以好好看看。-FPGA-based 16-bit multiplier, getting started can be a good look.
chengfaqi
- 通过verilog hdl语言实现伽罗华域GF（q）乘法器设计-By verilog hdl language Galois field GF (q) Multiplier
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器，除法器的设计-Achieved through verilog hdl adder multiplier, divider design
PLL_100M
- 实现pll分频功能倍频功能可得到fpga说需要的频率实现多的时钟输入-Multiplier pll divide function to achieve functionality available fpga said I need to achieve multi-frequency clock input
VHDL-
- 8位相等比较器，布斯乘法器，以为寄存器的VHDL实现-Eight for phase comparator, Booth multiplier, that registers of VHDL
matrix3x3_latest.tar
- 3X3 multiplier using hdl
High-quality-C-P-P-Programming-Guide
- 书中用对比的方式展示了良好的编程习惯、高质量的代码的重要性，结合作者的实践经验，是初学者必备，事半功倍提高编程水平的好书-Demonstrate good programming practice book with way of contrast, the importance of high-quality code, combined with the author' s practical experience, beginners must multiplier to impro
verilog-codes-for-booth2
- 由verilog编写的采用booth2编码的16*16乘法器-a 16*16 multiplier with booth2 coding by verilog
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori
clk_DCM_50to75MHz
- 调用ISE010.1的IP核DCM来实现频率倍增，本程序实现的是50MHz到75MHz的倍增，开发者可以根据DCM的参数设置实现不同频率的倍增-Call ISE010.1 IP core DCM to achieve frequency doubling, the program is 50MHz to 75MHz multiplication, developers can implement different parameter settings of DCM frequency mult
chengfaleijia
- verilog 乘法累加器 包括工程项目及仿真波形图-verilog multiplier-accumulator including the project and the simulation waveform
chengfaqi
- 基于fpga的乘法器设计 已经验证请放心下载-Fpga-based multiplier design has been verified, please rest assured download
Ex3_4
- 两个16位整数相乘，乘积总是“向左增长”，这意味着多次相乘后乘积将会很快超出定点器件的数据范围。而且要将32位乘积保存到数据存储器，就要开销2个机器周期以及2个字的程序和RAM单元；并且，由于乘法器都是16位相乘，因此很难在后续的递推运算中，将32位乘积作为乘法器的输入。然而，小数相乘，乘积总是“向右增长”，这就使得超出定点器件数据范围的是我们不太感兴趣的部分。在小数乘法下，既可以存储32位乘积，也可以存储高16位乘积，这就允许用较少的资源保存结果，也便于用于递推运算中。这就是为什么定点DSP芯
WT-PROGRAM
- wallence tree multiplier
exact_alm_rpca
- 用ALM实现 PCA算法，做模式识别的一看就懂，自己用的不错。-This matlab code implements the augmented Lagrange multiplier method for Robust PCA.
inexact_alm_rpca
- 非精确ALM解决PCA算法的例子，用后效果不错，发上来分享。-This matlab code implements the inexact augmented Lagrange multiplier method for Robust PCA.