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mux16
- 十六位乘法器的verilog hdl 实现 及 modelsim 仿真 环境为quartusii9.0 自动调用modelsim 6.5输出仿真结果-fpga verilog hdl modelsim quartusii 16-bit multiplier
Cpp1
- 大数据乘法，输入两个整数，正负均可，输出结果。-Big Data multiplier, input two integers, either positive or negative, the output result.
Text1
- 基于8051的频率计，使用stc的倍频功能可测至960kHz以上，同时可输出精确地自检信号，切换显示频率周期及显示锁定-Based on the 8051 frequency meter, using stc multiplier function can be measured to 960kHz or more, while self-test signal can be output accurately, the switching frequency cycles and displa
multt
- 该程序实现了一个16*16的乘法器，可以用作设计乘法器参考-The program implements a 16* 16 multiplier, multiplier design can be used as reference
PLUS_LIB
- 本程序实现九九乘法表的设计，九九乘法表系统能够自动或手动进行两个1位十进制数的乘法，并自动显示被乘数、乘数和乘积-This program is designed to achieve multiplication table, multiplication table system can automatically or manually two one decimal multiplication, and automatically displays the multiplicand,
4BITMUIT
- 利用LPM_MUIT宏模块设计一个四位数据乘法器-Use LPM_MUIT macro module design a four data Multiplier
MSP430F5438_example
- MSP430F5430例程,包括AD采集模块、时钟模块、乘法器、定时器、串口、看门狗等模块底层驱动源码 -MSP430F5430 routines, including driver source code of AD collection module, clock module, multiplier, timer, serial port, and watchdog module etc.
MultiplierHDL_FPGA
- Implementation of 4 bit array multiplier using Verilog HDL
ddc
- 数字下变频模块，顶层文件奇偶抽取，还有乘法器-Digital down conversion modules, top file parity extraction, there is a multiplier
Hardware_Multiplier
- 利用MSP430F149内部的硬件乘法器进行8bit-8bit，16bit-16bit的乘法，只需三个主时钟周期，即可读出运算结果。-Using MSP430F149 internal hardware multiplier for 8bit-8bit, 16bit-16bit multiplication, just three master clock cycles, you can read out the result of the operation.
Chapter-2
- 3.1加法树乘法器add_tree_mult设计实例, 3.2查找表乘法器lookup_mult设计实例. 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例 -3.1 adder tree multiplier add_tree_mult design example, 3.2 lookup table multiplier lookup_mult design examples. 3.3 Design Example 3.4 Bo
Chapter-3
- 3.1加法树乘法器add_tree_mult设计实例 3.2查找表乘法器lookup_mult设计实例 3.3布尔乘法器booth_mult设计实例 3.4移位除法器shift_divider设计实例-3.1 adder tree multiplier add_tree_mult design example 3.2 multiplier lookup_mult lookup table design example 3.3 Design Example 3.4 Boolean mu
Chapter-5
- 5.2 16位乘法器状态机实现 5.3 交通控制灯控制设计 5.4 PCI总线目标接口状态机设计-5.2 16 5.3 multiplier state machine traffic light control design 5.4 PCI bus target interface state machine design
N-bits-by-M-bits
- 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier
ARITHMETIC
- 算术乘法器，这是我自己设计的算术乘法器，是用VHDL语言设计的，希望对大家有帮助-Arithmetic multiplier, this is my own design arithmetic multiplier, is designed with VHDL language, and they hope to help everyone
FAT32_SD-Interface-C-function
- 在SD卡上实现FAT32文件系统，C实现，可程序结构清晰，简单易懂。里面还有一篇介绍FAT32文件系统的文档，学习代码之前，请耐心将pdf文档研读一遍，这样能达到事半功倍的效果-mplemented on the SD card FAT32 file system, C realized, program structure clear, simple and understandable. There is also a descr iption of the document FAT32 f
mux16
- 在该实验中就是要利用时序逻辑设计方法来设计一个16 位乘法器-In this experiment is to use sequential logic design method to design a 16-bit multiplier
Test_multiplier
- this is fast complex multiplier in vhdl
LQ_test_52259_PLLaUART
- mcf52259主MCU，串口、IO口等初始化功能，8M晶振倍频只144M-mcf52259 master MCU, Serial, IO ports and other initialization functions, 8M crystal multiplier only 144M
wallace_tree
- 华莱士树的硬件实现，多用于乘法器的加法运算部分-Wallace tree hardware implementation, used for the multiplier adder portion