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UART
- 實作UART 介面 4 byte 傳送 或 4 byte 接收 開發環鏡 quartus 且 附模擬檔-4 byte real interfaces for UART transmission or 4 byte receive loop mirror quartus and the development of simulation files attached
clk_div
- 用了20bit的计数器cnt，循环的计数，所以说一个周期有2的20次幂也即大约有1M分频，因为主时钟50MHz（周期就是20ns），所以20ms一个计数周期。蜂鸣器就以20ms的周期性发声，大家可以改变cnt的值看看效果。-quartus clock divided
BYTEBLASTERII
- byte blaster schematics for altera devices quartus software jtag programmer
Bufor
- Circular buffer using a cyclone memory ( Quartus II and VHDL .)-Circular buffer using a cyclone memory ( Quartus II and VHDL .)
DHT22_v1.1
- 我以前曾发过V1.0版的，这是此版的修正版v1.1,修正了以前版本中的一个错误，即只能读一个数据后就再也读不出温度数据的错误。 这个是用Quartus II软件写的Verilog HDL语言写的与温湿度传感器DHT2x通信的代码. 里面有详细的注解. 主要用于DHT2x单线总线通信转换为8位并行总线通信,应用于具有外部8位总线访问功能的单片机直接读取温湿度数据. 此程序在EPM7128SLC-10中成功测试. -I' ve once spoke V1.0 version, whic
CopyText
- 在使用quartus时.软件不支持中文输入. 使用小程序.在其中输入文本,然后在quartus中点击要输入的地方,进行拷贝即可.小程序自动清空.等待用户的下一次输入.-When using quartus. Software does not support Chinese character input. The use of small programs. In which the input text, and then click to enter quartus where cop
Stepper_controller_MAx
- stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable -stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog qu
KLAWIATURA_4x4_ZL9_VER2
- project is a simple keyboard 4x4 in VHDL in QUARTUS II from altera.com
sheji
- 基于Quartus的数字中设计（包含原工程），运行即可使用！-digitalclock
clock
- verilog 秒表程序（quartus ii8.2 ep2c5）-clock
vending
- vending machine for Quartus 8.1 version. verilog , vhdl code
registers
- 通用寄存器的VHDL代码，可以在quartus实现-General-purpose registers
SPYRAL
- quartus2 9.1版本的破解文件，绝对好用，我正在用。-quartus2 9.1 version of crack files, absolutely easy to use, I was using.
NIOSII_de2
- 基于SOPC的FPGA系统设计，测试数码管、LED、液晶显示屏，整个系统在DE2上运行通过，使用的是Quartus 6.1套件-FPGA-based SOPC system design, testing, digital tube, LED, LCD display, the entire system run by the DE2, using Quartus 6.1 Suite
EDA_Design_Repor_for_FIR_Filter
- 基于Quartus II的17阶FIR滤波器设计报告，详细介绍了从FIR滤波器原理到设计实现的全过程，适合学习。-Quartus II-based 17-order FIR filter design report, detailed from the realization of FIR filter theory to design the whole process, suitable for learning.
Work_with_Modelsim_SE_and_Quartus_II
- 仔细讲解了如何在Modelsim中建立Altera的仿真库(Verilog HDL)，如何使用Modelsim建立工程以及代码调试中的注意事项。-Carefully explained how to create Altera simulation Modelsim library, how to use Modelsim to establish engineering and debugging the code in the note.
VGA_Ctrl_VHDL
- 使用VHDL在Quartus II环境下实现对VGA接口显示器的控制，显示单色屏、彩条、棋盘格等。-The use of VHDL in the Quartus II environment to realize VGA interface display control, display monochrome screen, color bars, checkerboard grid and so on.
ug_altpll_reconfig
- Multiplicator using VHDL code in quartus -Multiplicator using VHDL code in quartus II
INTRODUCCION_INV_1_._OPER
- A introduction to VHDL yn quartus II
pc_2_quartus
- Pc2_quartus is a guie about VHDL anf quartus