搜索资源列表
Writing-Testbenches
- 如何写RTL的测试平台，仿真模型，进行系统验证。-Writing Testbenches-Functional Verification of HDL Models(2nd)
ALU
- verilog硬件仿真，实现32-bit RISC微处理器的算数逻辑单仿真元(ALU),实现加减运算、逻辑运算、移位运算。仿真级别为RTL级。-verilog hardware simulation, to achieve 32-bit RISC microprocessor arithmetic logic one simulation element (ALU), to achieve addition and subtraction operations, logic operations
rtl
- STOPWATCH,alarm,clock 功能的数字钟-General Digital Clock Clock setting with Switch – Use Key_up and Key_down key to change the number – Use Key_right and Key_left key to change the position – Use set key to start Clock Alarm Function – Use Ala
vmm_rtl_config
- 采用vmm rtl config的例子-Examples of using vmm rtl config
PWM_extend
- 本代码采用RTL级的硬件描述语言设计了一个多通道的PWM波形捕获、输出模块。主要用在无人机或是其它需要控制多个伺候电机的场合。开发环境为Xilinx公司的ISE12.0。-This code uses RTL-level hardware descr iption language designed a multi-channel PWM waveform capture, output module. Mainly used in the need to control multiple un
SPI
- 对SPI协议的RTL实现，相当典型的一个例子。包括时钟分频，移位逻辑等等。-the verilog for spi
switch_avr32
- Very low cost smart switch design. single atmega32 chip turns any RTL8309 based network switch into managed switch with all options supported by RTL chip. Switch can be accessed by telnet or com port.
6soft_247MHz_channel
- lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟
836335-IEEE-Standard-for-VHDL-Register-Transfer-L
- IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
1342563-IEEE-Standard-for-VHDL-Register-Transfer-
- 1076.6TM IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
switch
- It is switch design (RTL) implemented in verilog and have a verification environment in verilog
design-of-CAN-based-on-VHDL
- 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
the-verilog-source-code-of-8051-MCU
- 8051单片机的源代码,用verilog进行编写，包括测试文件-source code of 8051 MCU
VENDTEST
- 此为实现第14.7.9章所需的激励文件 该代码为门级RTL描述。-Stimulus file to verify Section 14.7.9 the functionality of gate vs. RTL descr iption.
FPGA
- 在数字电路的设计中，时序设计是一个系统性能的主要标志，在高层次设计方法中，对时序控制的抽象度也相应提高，因此在设计中较难把握，但在理解RTL电路时序模型的基础上，采用合理的设计方法在设计复杂数字系统是行之有效的，通过许多设计实例证明采用这种方式可以使电路的后仿真通过率大大提高，并且系统的工作频率可以达到一个较高水平。-In digital circuit design, timing design is a main indicator of performance in high-level
rtl
- led and 7segment with verilog
decimator
- Digital filter in delta-sigma ADC. But only work for RTL code now. Still have bugs in gate-level simulation.
VerilogDesignand-test_PdfPCode
- Verilog 设计与验证源码+PDF，经典教程，对与RTL和状态机的理解有很大帮助，适合FPGA开发工程师。-Verilog design and verification source+ PDF, classic tutorial, and state machine understanding of RTL helps a lot, suitable for the FPGA development engineers.
TFT-LCD-Controller_design-20080602
- TFT LCD控制器详细设计说明，包括架构设计，原理设计，RTL代码设计等-failed to translate
vlsi_script0607
- RTL Design Guideline E-Book