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VHDLProgramingLearn
- VHDL编程心得体会 包括进程、时钟、变量信号等应该注意的地方-VHDL process、Timer、signal and other things that is easy make mistake
led
- 定时器中断的例程,实现一秒定时,并在led灯上显示- Writes routine which a timer interrupts, realizes one second fixed time, and demonstrated on the led lamp
VHDL-0.1s-Timer
- 该程序完成了在altera de2 环境下实现0.1s新型计时器,该计时器可以运用于广大体育赛事中,有开关、暂停开始键、复位键。-The program completed the implementation in altera de2 0.1s under the new timer, which can be applied to the majority of sports events, a switch, pause start button, reset button.
0.01s-Timer-designed-in-VHDL
- 该设计方案是用VHDL语言实现0.01s计时器,该方案列出了详细的开发过程和所有源代码,并虽有仿真结果-The design solution is to use VHDL language 0.01s timer, the program lists the detailed development process, and all source code, and although the simulation results
Horloge_1_A
- Timer vhdl 24hours with alarm_setup CDSE_powaa !
VHDL-ALARM
- 要求设计一个带闹钟功能的24小时计时器 它包括以下几个组成部分: ① 显示屏:4个七段数码管显示当前时间(时:分)或设置的闹钟时间;一个发光二极管以1HZ的频率跳动,用于显示秒; ② 按键key1,用于设置调时还是调分; ③ 按键key2,用于输入新的时间或新的闹钟时间,每按下一次,时或分加1; ④ TIME(时间)键,用于确定新的时间设置; ⑤ ALARM(闹钟)键,用于确定新的闹钟时间设置,或显示已设置的闹钟时间; ⑥ 扬声器,在当前时钟时间与
timer
- 基于vhdl的单片机最小系统定时器模块。Timer模块-Timer Module
VHDL-Finished-Homework
- 有闹钟功能,可以定时的电子时钟,还可以设定定时时间-Have alarm clock function, the electronic clock timer, you can also set the regular time
4-BIT-TIMER
- VHDL code for four bit timer using J-K Flip flop
vhdl
- 基于PicoBlaze的实时时钟设计。PicoBlaze是Xilinx的8位软核。采用汇编语言编写。-Uart real timer
timer
- VHDL 实现定时器 嵌入式单片机 编程-VHDL Timer embedded microcontroller programming
timer
- 自己做的计时秒表VHDL语言程序,运行良好,一切俱全。-Own stopwatch VHDL language program, run good, all taste.
clock
- 数字计时器的vhdl实现,quartus 和 modelsim 仿真-Digital timer vhdl achieve quartus and modelsim simulation
Design-of-VHDL-based-digital-timer
- 基于VHDL的数字计时器的设计 基于VHDL的数字计时器的设计-Design of VHDL-based digital timer
VHDL
- 一些简单基本的vhdl代码源程序,包扩三八译码器,数据选择器,30s倒计时器等-Some simple basic VHDL source code procedures, bag expanding 38 decoder, data selector, 30 s down timer, etc
timer
- 定时器,VHDL 实现,希望对大家有用,共同学习-the timer with vhdl
timer
- 基于VHDL语言的一个简单秒表,包含按键消抖模块、数码管译码、计时器等模块。直接适用于basys2和nexys3两个开发板。更改ucf文件后适用于其他开发板-A simple stopwatch based on VHDL, including key debounce module, digital decoder, timers and other modules. Directly applicable to basys2 and nexys3 two development boards
Timer
- Nexys 3 seven segment display module written in VHDL
Top_LED_TUBE
- It is a timer VHDL code. The outputs are designed for 7-seg display.
7-timer
- 本代码是实现计算器的功能,用的是VHDL语言编写,全部实现过程都在这里面。-This code is to achieve the functions of the calculator, using the VHDL language, to achieve full process on the inside