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uart_verilog
- 包含UART口的VERILOG源程序,该程序在FPGA上验证通过,可作为芯片设计,或FPGA设计的一个完整IP核,硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
uart2bus
- uart接口到内部总线的IP核,采用VDHL和VERILOG语言编写。-UART interface to Bus IP Core in VHDL and verilog languages
uartnew
- 好用的UART通信源码,使用Verilog 编写 在QUARTUS下完成,并用ModelSim仿真通过-Source-to-use UART communications, the use of Verilog in Quartus to complete the preparation and use of ModelSim simulation through
WBUart
- Verilog实现的Uart模块,在quartus9.1环境下已综合、运行成功。-Verilog implementation Uart module has been integrated in the quartus9.1 environment, run successfully.
res232_top2
- 简单使用的uart串口程序,用verilog语言实现,在alteraDE2-70板上验证-Simple to use uart serial procedures, using verilog language, verified in alteraDE2-70 board
or1200_sopc
- 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram,最小系统soc。包括片上ram的软件系统(C语言编写)都有。但下载者要使用此系统需要很多工具链,搞soc的应该都装好了。 绝对原创!用quartusII11.0在Altera DE2-115上验证通过,Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating with each other in English. Ri
UART_FPGA_Code
- UART FPGA实现过程文档说明,及VERILOG HDL 代码,希望能帮助有需要的人,-UART FPGA implementation process documentation, and VERILOG HDL code, hoping to help people in need, thank you
uart_verilog
- Verilog HDL语言编写的uart程序,在别人基础上改动和优化完成,quartus ii 10.0编译通过,可综合,板上仿真通过。将PC机发送的字符串发送回,可一次发送多个字符串。-Verilog HDL language uart program, in others on the basis of changes and optimization is complete, quartus ii 10.0 compiler, integrated, on-board through si
uart_latest.tar
- 串口(UART)的verilog源代码,可以供设计参考-Serial port (UART) of the Verilog source code, can be used for reference in design
uart_io_test
- verilog中UART的PC通信协议,看过的人都说好,已经验证正确性,很不错的代码。-verilog in the PC UART communication protocols, seen people say well, has verified the accuracy, very good code.
uart_ps2
- ps2接口的verilog module 负责用键盘发送数据,附带仿真task仿真,代码简单明了。 uart接口的verilog module ,通过PC机上的串口助手接收并显示键盘发送的数据 FPGA 板调试OK-ps2 verilog module with uart verilog module,fpga simulation ok.ps2 send data and uart get data and display in PC
uart_rx
- a verilog code to receive data in uart standard
traffic_controller
- 一款交通灯控制芯片的verilog源码,该源码通过仿真并在FPGA上运行成功,可以实现上位机操作控制交通灯的工作模式:两相模式和四相模式。上位机操作通过串口调试助手来完成。源码中与上位机的接口采用的是UART接口。-This is a verilog code for a kind of traffic light controller. The code was simulated and verificated on FPGA. When the code works on FPGA, it