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multi_cpu
- 用verilog语言编写的简单多周期CPU代码，在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。-Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction.
pipeline10
- 用verilog实现嵌入式系统的处理器的五级流水线。-realizing the five stages of cpu in the embedded system with the verilog language
cpu_design
- FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
cpu5.10_modelsim
- 用verilog编写的8位最简cpu代码，能实现简单的加减运算，存储运算，以及寄存器操作。-Verilog prepared with 8 simple CPU code, to achieve a simple addition and subtraction, memory operations, as well as register operations.
Project-8
- 课程设计时用verilogHDL写的MIPS CPU-MIPS CPU coded with Verilog HDL
computer-composition
- Verilog在FPGA上实现多周期流水线带forwarding和hazard检测(如果你是学弟，为你着想，请不要直接copy)-Verilog on FPGA implementing a multi-cycled CPU with forwarding and hazard test
ECOP-13349069-03
- verilog语言实单周期cpu的设计，已经用ise测试、仿真通过。-verilog single cpu
cpu_1
- 用verilog设计五级CPU的框架，需要自己另行补充指令，可作为学生作业和训练内容-Five CPU with verilog design framework, needs its own separate supplemental instruction can be used as student assignments and training content
EPM3032
- EPM3032上使用quartus5.0编写的verilog程序，用于单片机译码并驱动外设之用。-A verilog program used for embeded cpu encode and drive pheripha chip,platform is quartus5.0
openfire_core_latest.tar
- openfire实现 microblaze机构的cpu代码,RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡-openfire complete microblaze architecture cpu,RISC CPU Verilog sourcecode and documents
Project6(finish)
- modelsim下仿真通过，用Verilog写的多周期CPU，是计算机组成原理的大作业，供学弟学妹参考。-Under modelsim simulation by using Verilog write multi-cycle CPU, is composed of a large computer operating principle for mentees reference.
risc8
- 八位简易risccPU，采用verilog描述，FPGA实现-8bit risc CPU
MIPSCPUverilog
- mips流水线CPU的实现，用的是verilog语言，描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
SRC
- 流水线CPU的verilog实现，包含id，if，ex，mem等部分的源码-an implementation of Pipelined CPU in verilog
cpu_verilog
- cpu的verilog描述的代码。比较适合初学者，-cpu verilog descr iption of the code. More suitable for beginners,
RISC_CPU
- RISC cpu设计，verilog语言，PIC14位指令集-RISC cpu design, verilog language, PIC14-bit instruction set
mips16e.tar
- 使用verilog HDL编写的mips16e 16位cpu，按照mips16e官方说明编写-Use verilog HDL prepared mips16e 16 位 cpu, the official note has been prepared in accordance with mips16e
0340196Lab3
- 这是用Verilog语言编写的带有pipeline功能的CPU，适合于学习计算机组织的同学-This is a Verilog language functions CPU with pipeline for students to learn computer organization
8BIT_CPU
- 一个8位的CPU设计，用verilog语言写的，希望有用-A CPU OF 8 BITS
A_CPU_verilog
- 这是一个verilog编写的CPU程序，希望对初学者有所帮组吧-a cpu