搜索资源列表
ser_adder
- 串入串出加法器 verilog 代码 串入串出加法器 verilog 代码-serial adder verilog code serial adder verilog code
my_half_add
- 基于FPGA的半加器源码，声明，有verilog编写的-FPGA-based half adder source, statement, written in verilog
fVerrilog_Devr
- 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
ripple_carry_adder
- 行波加法器，Verilog语言编写。行波加法器，Verilog语言编写-The line wave adder Verilog language. The line wave adder Verilog language
float
- 基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
carrylook4bit
- carry 4-bit adder program in verilog
d10-counter
- 十位加法器，用verilog语言编写，适用于verilog学习。-10-bit adder, using Verilog language, applicable in verilog learning.
add
- FPGA VERILOG 加法器，数码管显示-FPGA VERILOG the Adder, digital tube display
add_ded_module
- 使用Verilog语言编写的4位加减法器，经验证能在FPGA开发板上实现。-Verilog4 bit adder-subtractor.
add
- 用verilog实现加法器程序，通过仿真验证-Adder verilog achieve program is verified by simulation
carry_select
- 上传的代码是基于Xilinx下的ISE开发平台，用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.
float
- 32位浮点加法器 verilog语言编写-32-bit floating-point adder verilog language
lbq3
- 滤波器的verilog代码 主要是对算法的折叠 有原先的4个加法器四个乘法器变成2个加法器两个乘法器-Filter verilog code folding algorithm 4 adder four multipliers into two adders and two multipliers
full_add
- 这个是用verilog语言写的一个全加器的程序-This is to use verilog language to write a full adder program
ADD
- Verilog编写的Altera单精度加法器源码-Altera single precision adder source Verilog prepared
test
- the carry save adder program in verilog
xjwbwd
- 这个fpadd程序应用verilog语言，实现的功能是简单的浮点加法器。初学的同学们可以一看。-This fpadd program applications verilog language to achieve the function is simple floating point adder. Beginner students can have a look.
add
- 加法器的verilog代码希望对需要的人起一定的参考-Adder verilog code hope for those who need to play a certain reference
code
- 32位全加器 使用verilog写的硬件描述语言，xilinx芯片上运行过-32bits full adder
code
- 32bits流水线加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits pipelined adder verilog language, xilinx chip run through