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FifoAndTestbench
- 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
Verilog_USB_OUT
- USB out，使用Verilog写的，包含完整工程、文档和USB芯片的固件-USB OUT, VERILOG, Including project、document，USB firmware
fifo_tb
- verilog implementation of 16X4 fifo with testbench
fifo_verilog
- 用verilog 实现 fifo，宽度按自己需求扩展-Achieved with the verilog fifo, the width of expansion according to their needs
AsynFIFO
- Verilog 代码 异步FIFO，可综合，综合效率高，cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
syn_fifo
- 基于systemverilog的异步fifo-fifo of design ，system verilog
asy_fifo
- 用verilog实现异步fifo，通过仿真-Asynchronous with verilog fifo, the simulation
fifo
- 采用verilog HDL语言实现FIFO的功能，内涵测试程序，有较强的使用性能。-Using verilog HDL language to achieve FIFO functionality, meaning the test program, there is a strong performance.
FIFO
- 此程序为verilog语言，实现的功能为FIFO功能，包括三个部分，分别实现不同的功能。-This program is verilog language, functions as a FIFO function, consists of three parts, respectively, to achieve different functions.
FIFO
- verilog 实现FIFO存储功能，八位数据宽度，16数据深度。-verilog achieve FIFO memory functions, eight-bit data width, the depth of 16 data.
fifo
- 使用verilog实现FIFO，包含所有工程文件。-Verilog implementation using FIFO, includes all project files.
FIFO-Design
- FIFO(first in first out)-first in first out, using verilog
Fifo_lk
- 简单好用的Fifo 128x32 Verilog-Fifo 128x32 Verilog
FIFO-verilog
- 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design,
Asynchronous-FIFO-Design
- 异步FIFO设计，一共包含6个模块，使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
FIFO
- FIFO的设计，用Verilog HDL语言编写-The design of FIFO,using Verilog HDL program language
FIFO
- 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
fifo
- 利用verilog来实现fifo的读写，并有testbench程序。-fifo verilog
fifo-verilog
- 用verilog 编写的fifo（先入先出队列）代码 内含测试文件 test bench-First Input First Output programme which designed by verilog codes,including test bench
FIFO
- Verilog代码，实现FIFO先入先出存储-FIFO CODE,VERILOG