搜索资源列表
PCI-IPcoreor1k[1]
- PCI的ip core,VHDL代码,希望对大家有帮助-PCI-ip core, VHDL code, we hope to help
IPcore
- 基于EP3C25的Altera SDI IP核的使用-EP3C25 Altera SDI IP
uartvhdl
- VHDL语言实现的UART IP核,比较实用-VHDL language to achieve the UART IP core, more practical
aes_inv_cipher_top
- aes ip core, 128 bits
FFT_verilog
- verilog实现的FFT变换,经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
ethernet
- 以太网MAC层IP核设计Veriolg代码,包括TESTBECH平台和设计文档-Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents
HDLC
- verilog HDL语言编写的HDLC协议的IP核,包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
USB2.0IP(RTL)
- USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
Verilog_UDP
- 辛辛苦苦找到的UDP的资料,在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段,在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西,希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-de
altera_up_avalon_sram
- 基于Avalon的SDRAM控制器IP核-Avalon SRAM Controller
ARMcore
- 基于FPGA的ARM IP核!该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
fft
- 基于VHDL语言编写的FFT程序,256点,旋转因子存在自己编写的ROM里面,乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
a8254
- 基于8254 ip 核的vhdl的实现以及对于quart 2的实现及应用-Based on the 8254 IP core of the realization of VHDL and for the implementation and application quart 2
SPI
- 经典spi IP 核心 FPGA是实现有说明文档-spi IP based on fpga
BlockRAM
- xilinx BlockRAM 级联,利用Xilinx原语(非IP Core),更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
hdlc
- HDLC协议的VHDL源码。接收和发送模块,以及所用FIFO的IP核(Xilinx公司)。-The code of HDLC protocol.Receive and transmit module is contained.
pci_core.tar
- vhdl 写的 PCI IP核程序,已经过测试-pci ip core
vga_game_demo
- 乒乓球游戏,基于Xilinx板子,并且有vga IP核,使用EDK进行编程-Table Tennis Games
freerisc8_11
- 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
ramvhdllib_06
- The Free IP Project VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core