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fifo
- 异步fifo的verilogHDL代码 通过比较读写地址并产生异步空/满标志，再通过把异步空/满标志同步到相应时钟域来实现数据的传递。很好的解决了亚稳态的问题。-code of asynchronous fifo
Flag-of-asynchronous-FIFO
- Quartus平台，VHDL代码编写的带标志位的异步FIFO。-Quartus platform, VHDL code is written with the sign bit of the asynchronous FIFO.
Asynchronous-FIFO-Design
- 异步FIFO设计，一共包含6个模块，使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
FIFO
- 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
fifo
- 异步FIFO源代码，由模块调用自动生成，不包含测试向量。-Asynchronous FIFO source code automatically generated by the module calls, does not contain the testbench.
FIFO
- FPGA内设计同步FIFO和异步FIFO，以及双口RAM的方法,FIFO设计的经验之谈，非常经典。-Synchronous FIFO and asynchronous FIFO, and dual-port RAM within the FPGA design,FIFO design rule of thumb, very classic.
FIFO
- Verilog HDL语言编写异步FIFO-Verilog HDL language, asynchronous FIFO
FIFO
- 异步FIFO设计 FPGA代码 Asynchronous fifo-Asynchronous fifo
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
FPGA-FIFO-VHDL
- 这是一个基于FPGA的异步FIFO设计，利用的VHDL硬件描述语言，内容分析清楚，附带完整代码-This is an FPGA-based asynchronous FIFO design, the use of VHDL hardware descr iption language, content analysis, with complete code
fifo
- 本文档是一个异步FIFO设计的完整工程，利用modelsim仿真软件，分不同的模块-This document is the complete works of an asynchronous FIFO design, the use of the modelsim simulation software, divided into different modules
Asynchronous-FIFO-structureadesign
- 异步FIFO结构和FPGA设计，首先介绍异步FIFO的概念、应用及其结构，然后分析实现异步FIFO的难点问题及其解决办法；在传统设计的基础上提出一种新颖的电路结构并对其进行综合仿真和FPGA实现-The asynchronous FIFO structure and FPGA design, first introduced the asynchronous FIFO concept, application, and its structure, and then analyze the as
Async-FIFO-VHDL
- 异步FIFO VHDL代码实现，包括：async_fifo_show_ahead.vhd， async_fifo_show_ahead_rd_task_logic.vhd，async_fifo_show_ahead_wr_task_logic.vhd， sync_r2w.vhd，sync_ram_std_dc.vhd，sync_w2r.vhd-The asynchronous FIFO VHDL code implementation, including: async_fi
FPGA-FIFO
- FPGA-跨时钟域总线信号可靠传输异步FIFO技术安全可靠，格雷码计数，减少亚稳态-FPGA-clock domain crossing bus signals reliable transmission of asynchronous FIFO safe and reliable, Gray code count, reducing the metastable
FIFO
- 用VHDL语言实现一种异步FIFO，并做时序仿真和功能仿真检验正确性。-Achieve an asynchronous FIFO using VHDL language, and do functional simulation and timing simulation test accuracy.
fifo
- 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
FIFO
- 关于异步FIFO的原码程序，采用格雷码改善了二进制码带来的不足- ON划词翻译ON实时翻译 On asynchronous FIFO the original code procedures, the use of gray code improves deficiency caused by binary code
fifo
- 同步fifo和异步fifo程序，含时钟同步。运用格雷码-Synchronous FIFO and asynchronous FIFO FIFO procedures, including clock synchronization. Application of gray code
FIFO
- 利用verilog写的异步FIFO的一种写法-Using a written verilog write asynchronous FIFO