搜索资源列表
APDLL
- 数字锁相环的FPGA设计与实现，用maxplus2实现的-DPLL FPGA design and implementation, with maxplus2 achieve
a-adpll-based-on-fpga
- FPGA实现的VHDL语言的全数字锁相环-a adpll based on fpga
cx
- 变模可逆计数器的VHDL功能描述，是数字锁相环的一个期间的程序-Reversible counter variable mode
count_zj
- 基于FPGA的数字锁相环中环路滤波器的设计-FPGA digital PLL loop filter design
pplllrarl
- 用VHDL写的数字锁相环程序源码 pll.vhd为源文文件 pllTB.vhd为testbench 可直接使用。 -Written using VHDL digital PLL pll.vhd program source code for the source text file pllTB.vhd testbench can be used directly.
FdplllzipP
- ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ -FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
dpll1600e
- 数字锁相环的设计，包括鉴相器，环路滤波器，spi口输出，分频器的源代码-Digital phase-locked loop design source code, including the phase detector, loop filter, spi port output divider
Programmoing
- 51单片机及其C语言程序开发实例,介绍了51单片机常用的模块电路设计与实现，主要模块有键盘、LCD显示、A/D转换、D/A转换、I2C总线应用、语音、实时时钟、红外、USB、步进电机、数字锁相环、串口通信、DDS等-51 microcontroller C language program development instance, introduced 51 single-chip module circuit design and implementation of the main mod
PLL_continious
- 数字锁相环，matlab仿真模型，用PID实现-digital PLL,MATLAB simulation module
ver3
- 全数字锁相环的verilog代码，希望能有帮助-The DPLL verilog code, hoping to help! ! !
PLL
- 基于TMS320F28335的全数字锁相环的设计-The design of the digital PLL based on TMS320F28335
verilog
- 全数字锁相环的verilog源代码，用于FPGA开发全数字锁相环-DPLL verilog source code for FPGA development DPLL
suoxiang
- 电力并网数字锁相环(PLL)程序，简单可靠 -Electricity grid digital phase-locked loop (PLL) program, a simple and reliable
DCO_ST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
DPLL_TEST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
DLF
- 可增可减的计数器，可以用于全数字锁相环中的环路低通滤波器-Either upwards or downwards counter low-pass filter can be used for all-digital phase-locked loop in the loop
paper3
- MPSK解调的关键在于载波同步和码元同步．这里采用 数字锁相环实现载波同步和码元同步.pdf-MPSK demodulation key symbol synchronization and carrier synchronization. Here digital phase-locked loop carrier synchronization and symbol synchronization. Pdf
PLL
- 三相数字锁相环pscad仿真 dq算法 PI控制-Three-phase digital phase-locked loop simulation in pscad
PLL_success
- 数字锁相环，曼彻斯特的产生与解码,verilog hdl-Digital PLL, Manchester generation and decoding, verilog hdl
dpll2
- 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider