搜索资源列表
test
- VHDL语言实现数字锁相环，方法为超前滞后法-VHDL language digital phase-locked loop, and methods for lead-lag method
pll1
- 数字锁相环matlab编程代码，适用于初学者进行参考，欢迎大家下载！-Digital phase-locked loop matlab programming code, suitable for beginners reference, welcome to download
PLL
- 一种基于数字锁相环的matlab的程序仿真代码-Based on digital phase-locked loop matlab simulation
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
pll_zsy.v
- 全数字锁相环程序 此程序基于VHDL编写 可以完成相关功能-All digital phase-locked loop based on VHDL write program this program can complete the relevant function
DPLL
- 一个全数字锁相环，可用于信号的复用中，进行调制和借条操作。-A digital phase-locked loop can be used to signal multiplexing, modulation and IOU operations.
ADPLL
- verilog语言编写的fpga的全数字锁相环ADPLL程序-Verilog language FPGA all digital phase-locked loop ADPLL program
dpll3
- 数字锁相环 VERILOG语言编写的基于FPGA平台的PLL程序-VERILOG language based on the FPGA platform PLL program
DPLL_Stability_ConstantBW
- matlab代码：计算数字锁相环中数字滤波器的参数，满足稳定性和环路带宽要求。-matlab code: calculate the parameters of DLF in DPLL to meet the specific loop bandwidth and stability.
threephasepll
- 实现三相交流信号的相位跟踪功能，三相数字锁相环，matlab simulink程序。-matlab simulink three phase
[emuch.net]PhaseLockedLoo
- 各种Pll的Simulink建模与仿真，包括线性模拟锁相环，全数字锁相环，带电荷泵的锁相环。建平鉴相器子系统建模-PLL simulation based on Matlab Simulink
UART_DPLL
- 通过串口uart rs232控制的全数字锁相环，dpll， 可锁时钟相位-UART CTORLER DPLL MODULE CLK
YD
- 运用qurtus9.0进行全数字锁相环的制作，内含有各个模块及程序注释。-Of all digital phase-locked loop with qurtus9.0 production, contains various modules and application notes
dpll
- 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis
pll_tools
- 封装的matlab程序，实现数字锁相环的工具(Encapsulated matlab program, a tool for implementing a digital PLL)
pll
- 封装的matlab程序，实现数字锁相环的功能函数(Encapsulated matlab program to implement the function function of the digital PLL)
Phase Locked Loop2
- 数字锁相环锁定相位一致，调控频率的功能函数(The function function of the locking phase of the digital PLL and the frequency control)
CEUZRZQ
- 实现4阶数字锁相环,老外写的,有详细注释,如果您觉得不错,就re一下()
KEXQ30
- 关于数字锁相环方面的代码,觉得还可以,或许对大家有用()
基于DSP的60kW_300kHz高频感应加热电源
- 介绍了一种基于DSP 的高频感应加热电源。现以MOSFET为开关器件，并通过逆变器并联扩容为60kW/300kHz。采用多重斩波技术，增大了斩波电路的容量，将基于DSP 的fuzzy-DPLL 复合数字锁相环技术应用在高频场合，使锁相有快速的动态性能和高精度的稳态性能，实现了对负载频率的可靠跟踪及对逆变状态的可靠控制，提高了逆变器 的工作效率和功率因数。(A high frequency induction heating power supply based on DSP. MOSFET i