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costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
costas_loop
- costas环载波同步与解调，其中有环路滤波器系数估算-costas loop carrier synchronization and demodulation, including the loop filter coefficients estimation
Phase_Noise
- matlab对PLL环路相位噪声的仿真m文件-simulation of PLL loop phase noise
dsdv
- ns2下dsdv实现代码。DSDV（Destination-Sequenced Distance-Vector）协议是先应式路由协议，是由传统的Bellman-Ford 路由协议改进得到的，其特点是利用目的节点序列号解决了DBF算法的路由环路和无穷计数问题。-dsdv the realization of the code under ns2. DSDV (Destination-Sequenced Distance-Vector) protocol is proactive routing p
LDPC_H_Construction
- LDPC码H矩阵构造的三种尝试，包括比特填充法、PEG法和近似最短环路法（ACE）的实践-This document includes three methods to implement LDPC H matrix construction. Please enjoy them!
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
frequencySynthesis
- 频率合成器环路滤波器的设计，介绍由集成锁相芯片PE3236 和集成锁相芯片ADF4107 组成的单环锁相环常用的环路滤波器。-Frequency synthesizer loop filter design, introduced by the integrated phase-locked-chip phase-locked PE3236 and an integrated single-chip component Central ADF4107 PLL loop filter common
loop
- 对锁相环路的仿真，二阶环的仿真与分析都可以通过这个文件来到完成-Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came
carrier_nco
- 通信电路中产生载波的电路，可应用于GPS中的捕获和跟踪环路。-Generated carrier communication circuit of the circuit, can be applied to GPS in the capture and tracking loop.
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of
nfenpin
- N分频器则是一个简单的除N 计数器。分频器对脉冲加减电路的输出脉冲再进行N分频，得到整个环路的输出信号Fout。-N divider is a simple addition to N counter. Addition and subtraction of the pulse divider circuit output pulse frequency N again, the whole loop of the output signal Fout.
FPGAphaselockedloopdesign
- 介绍了应用VHDL技术设计嵌入式全数字锁相环路的方法，详细叙述了其工作原理和设计思想，并用可编程逻辑器件FPGA实现。-Introduce the application of VHDL technical design embedded DPLL road approach, described in detail its working principle and design idea, and programmable logic device FPGA implementation.
awewq
- 直扩接收机同步跟踪环路的研究与改进 这是付费资源库里面资源哦 -nice
phase-locked
- 主要是关于锁相环的环路滤波设计与计算，非常经典的-Mainly on the phase-locked loop filter design and calculation, very classic
kruskal1
- kruskal算法求解最小生成树 K r u s k a l算法每次选择n- 1条边，所使用的贪婪准则是：从剩下的边中选择一条不会产生环路的具有最小耗费的边加入已选择的边的集合中。注意到所选取的边若产生环路则不可能形成一棵生成树。K r u s k a l算法分e 步，其中e 是网络中边的数目。按耗费递增的顺序来考虑这e 条边，每次考虑一条边。当考虑某条边时，若将其加入到已选边的集合中会出现环路，则将其抛弃，否则，将它选入。-kruskal
Interlooptestingbulkendpoint
- 批量端点间环路测试，用KEIL编写，适用于CY7C68013学习板的测试和开发-Inter-loop testing bulk endpoint, using KEIL prepared for the test board CY7C68013 learning and development
Interruptionoftheuseofendtolooptesting
- 利用端点中断进行环路测试，在KEIL中运行，适用于CYUSB的开发和仿真-Interruption of the use of end-to-loop testing, in KEIL run for the development and simulation CYUSB
VolumebetweentheendpointandexternalRAMtestloop
- 批量端点间和外部RAM环路测试，在KEIL中运行，适用于CYUSB的开发和仿真-Volume between the endpoint and external RAM test loop, in KEIL run for the development and simulation CYUSB
Kruskal
- 本文件是数据结构中很重要的一个图的Kruskal算法。Kruskal算法每次选择n- 1条边，所使用的贪婪准则是：从剩下的边中选择一条不会产生环路的具有最小耗费的边加入已选择的边的集合中。将文件编译，可完成Kruskal算法-This document is a very important data structure of a graph algorithm of Kruskal. Kruskal algorithm for each choice of n-1 edges, the gre
SysgenQAM16Demodulation
- 采用Xilinx的Sysgen工具建立的16QAM调制解调模型，其中包括信源生成、多普勒频偏、载波跟踪环路等。-Established by the use of Simulink model of 16QAM modulation and demodulation, including source generation, Doppler shift, such as carrier tracking loop.